{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,25]],"date-time":"2026-04-25T08:31:30Z","timestamp":1777105890585,"version":"3.51.4"},"reference-count":26,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2011,2]]},"DOI":"10.1109\/hpca.2011.5749714","type":"proceedings-article","created":{"date-parts":[[2011,4,18]],"date-time":"2011-04-18T09:49:44Z","timestamp":1303120184000},"page":"25-36","source":"Crossref","is-referenced-by-count":86,"title":["Thread block compaction for efficient SIMT control flow"],"prefix":"10.1109","author":[{"given":"Wilson W. L.","family":"Fung","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Tor M.","family":"Aamodt","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/1543753.1543756"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/SC.2010.51"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2000.898067"},{"key":"ref13","first-page":"140","article-title":"Rigel: An Architecture and Scalable Programming Interface for a 1000-core Accelerator","author":"kelrn","year":"2009","journal-title":"Proc Int l Symp Computer Arch (ISCA)"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2004.1310763"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/800031.808581"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2008.31"},{"key":"ref17","author":"lindholm","year":"2010","journal-title":"Across-Thread Out-of-Order Instruction Dispatch in a Multithreaded Microprocessor (Assignee NVIDTA Corp )"},{"key":"ref18","author":"mahesri","year":"2009","journal-title":"Tradeoffs in Designing Massively Parallel Accelerator Architectures"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2008.4771788"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/PROC.1972.8647"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2009.4919648"},{"key":"ref6","article-title":"Convergence of Recognition, Mining, and Synthesis Workloads and its Implications","volume":"96","author":"chen","year":"2008","journal-title":"Proceedings of the IEEE"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC.2009.5306797"},{"key":"ref8","article-title":"Tracking Register Usage During Multithreaded Processing Using a Scorebard having Separate Memory Regions and Storing Sequential Register Size Indicators (Assignee NVIDIA Corp.)","author":"coon","year":"2008"},{"key":"ref7","article-title":"System and Method for Managing Divergent Threads in a SIMD Architecture (Assignee NVIDIA Corp.)","author":"coon","year":"2008"},{"key":"ref2","year":"2009","journal-title":"R700-Family Instruction Set Architecture"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.30"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/1572769.1572792"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/1815961.1815992"},{"key":"ref22","year":"2009","journal-title":"Nvidia's Next Generation CUDA Compute Architecture Fermi"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1145\/1365490.1365500"},{"key":"ref24","year":"2010","journal-title":"NVIDIA CUDA Programming guide"},{"key":"ref23","year":"2009","journal-title":"Nvidia Compute PTX Parallel Thread Execution ISA Version 1 4"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1186\/1471-2105-8-474"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1002\/jcc.20289"}],"event":{"name":"2011 IEEE 17th International Symposium on High Performance Computer Architecture (HPCA)","location":"San Antonio, TX, USA","start":{"date-parts":[[2011,2,12]]},"end":{"date-parts":[[2011,2,16]]}},"container-title":["2011 IEEE 17th International Symposium on High Performance Computer Architecture"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5743111\/5749710\/05749714.pdf?arnumber=5749714","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,21]],"date-time":"2017-03-21T03:15:13Z","timestamp":1490066113000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5749714\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,2]]},"references-count":26,"URL":"https:\/\/doi.org\/10.1109\/hpca.2011.5749714","relation":{},"subject":[],"published":{"date-parts":[[2011,2]]}}}