{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,18]],"date-time":"2025-11-18T12:13:44Z","timestamp":1763468024932,"version":"3.28.0"},"reference-count":34,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2011,2]]},"DOI":"10.1109\/hpca.2011.5749715","type":"proceedings-article","created":{"date-parts":[[2011,4,18]],"date-time":"2011-04-18T13:49:44Z","timestamp":1303134584000},"page":"38-49","source":"Crossref","is-referenced-by-count":12,"title":["Low-voltage on-chip cache architecture using heterogeneous cell sizes for high-performance processors"],"prefix":"10.1109","author":[{"given":"Hamid Reza","family":"Ghasemi","sequence":"first","affiliation":[]},{"given":"Stark C.","family":"Draper","sequence":"additional","affiliation":[]},{"given":"Nam Sung","family":"Kim","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/T-ED.1979.19370"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1978.1051122"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.897148"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2008.4523220"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2008.4771813"},{"key":"ref10","doi-asserted-by":"crossref","first-page":"92","DOI":"10.1145\/1105734.1105747","article-title":"Multifacet's general execution-driven multiprocessor simulators (GEMS) toolset","volume":"33","author":"martin","year":"2005","journal-title":"Computer Architecture News"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ESSDER.2004.1356522"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.859025"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2008.4585947"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1978.1051122"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2010.5647605"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2004.1289279"},{"year":"0","key":"ref17"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.888357"},{"key":"ref19","doi-asserted-by":"crossref","first-page":"109","DOI":"10.1535\/itj.1002.03","article-title":"Power and thermal management in the Intel® Core Duo Processor","volume":"10","author":"naveh","year":"2006","journal-title":"Intel Technology Journal"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2007.4342738"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2008.22"},{"key":"ref27","first-page":"328","article-title":"A 65nm 8T sub-Vt SRAM employing sense-amplifier redundancy","author":"verma","year":"2007","journal-title":"Proc IEEE Int Solid-State Circ Conf"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/DSD.2007.4341526"},{"key":"ref6","first-page":"488","article-title":"The asynchronous 24-MB on-chip level-3 cache for a dual-core Itanium® family processor","author":"wuu","year":"2006","journal-title":"In Proc of IEEE Int Solid-State Circuit Con"},{"key":"ref29","first-page":"252","article-title":"A 5.3GHz 8T-SRAM with operation down to 0.41V in 65nm CMOS","author":"chang","year":"2007","journal-title":"Proc Symp VLSI Circuits"},{"key":"ref5","first-page":"166","article-title":"Fuse area reduction based on quantitative yield analysis and effective chip cost","author":"garg","year":"2006","journal-title":"In Proc of IEEE Int Symp on Defect and Fault Tolerance in VLSI Sys"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669126"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669128"},{"year":"0","key":"ref2"},{"key":"ref9","first-page":"30","article-title":"Evaluating non-deterministic multi-threaded commercial workloads","volume":"38","author":"alameldeen","year":"2002","journal-title":"In Proc of Workshop on Compo Arch Evaluation Using Commercial Workloads"},{"key":"ref1","article-title":"Variability and SRAM design","author":"clinton","year":"2008","journal-title":"IEEE Int Solid-State Circuit Conf Microprocessor Foru"},{"year":"0","key":"ref20"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/2.982916"},{"key":"ref21","article-title":"Scheduling for reduced CPU energy","volume":"1","author":"weiser","year":"1994","journal-title":"Proc USENIX Symp on Operating System Design and Implementation"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1145\/1283780.1283790"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1145\/1736020.1736036"},{"year":"0","key":"ref26"},{"year":"0","key":"ref25"}],"event":{"name":"2011 IEEE 17th International Symposium on High Performance Computer Architecture (HPCA)","start":{"date-parts":[[2011,2,12]]},"location":"San Antonio, TX, USA","end":{"date-parts":[[2011,2,16]]}},"container-title":["2011 IEEE 17th International Symposium on High Performance Computer Architecture"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5743111\/5749710\/05749715.pdf?arnumber=5749715","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,19]],"date-time":"2017-06-19T22:50:12Z","timestamp":1497912612000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5749715\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,2]]},"references-count":34,"URL":"https:\/\/doi.org\/10.1109\/hpca.2011.5749715","relation":{},"subject":[],"published":{"date-parts":[[2011,2]]}}}