{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,5,21]],"date-time":"2025-05-21T06:56:07Z","timestamp":1747810567104,"version":"3.28.0"},"reference-count":43,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2011,2]]},"DOI":"10.1109\/hpca.2011.5749741","type":"proceedings-article","created":{"date-parts":[[2011,4,18]],"date-time":"2011-04-18T09:49:44Z","timestamp":1303120184000},"page":"333-334","source":"Crossref","is-referenced-by-count":17,"title":["Calvin: Deterministic or not? Free will to choose"],"prefix":"10.1109","author":[{"given":"Derek R","family":"Hower","sequence":"first","affiliation":[]},{"given":"Polina","family":"Dudnik","sequence":"additional","affiliation":[]},{"given":"Mark D.","family":"Hill","sequence":"additional","affiliation":[]},{"given":"David A.","family":"Wood","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1145\/1360612.1360617","article-title":"Larrabee","volume":"27","author":"seiler","year":"2008","journal-title":"ACM Transactions on Graphics"},{"year":"2002","key":"ref38","article-title":"The Economic Impacts of Inadequate Infrastructure for Software Testing"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2006.1598132"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1145\/1508244.1508256"},{"key":"ref31","doi-asserted-by":"crossref","first-page":"284","DOI":"10.1145\/1080695.1069994","article-title":"BugNet: Continuously Recording Program Execution for Deterministic Replay Debugging","author":"narayanasamy","year":"2005","journal-title":"Proc 32nd International Symp on Computer Architecture"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1145\/1168857.1168886"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1145\/166955.166979"},{"key":"ref36","first-page":"168","article-title":"Improving the Throughput of Synchronization by Insertion of Delays","author":"rajwar","year":"2000","journal-title":"Proc Int Symp High Performance Computer Architecture (HPCA)"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1145\/1080695.1070011"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1145\/859618.859632"},{"journal-title":"Parallel Computer Architecture A Hardware\/Software Approach","year":"1999","author":"culler","key":"ref10"},{"journal-title":"SPARC Architecture Manual (Version 9)","year":"1994","author":"weaver","key":"ref40"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/1508244.1508255"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/125826.125941"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/1060289.1060309"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/1346256.1346273"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/1403375.1403735"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/1278177.1278181"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/40.848474"},{"article-title":"TSOtool: A Program for Verifying Memory Systems Using the Memory Consistency Model","year":"0","author":"hangal","key":"ref18"},{"article-title":"Racey: A Stress Test for Deterministic Execution","year":"0","author":"hill","key":"ref19"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1145\/1508244.1508254"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/SUPERC.1990.130019"},{"article-title":"DeLorean: Recording and Deterministically Replaying Shared-Memory Multiprocessor Execution Efficiently","year":"0","author":"montesinos","key":"ref27"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2005.41"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/1454115.1454128"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2006.1598134"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/1736020.1736029"},{"key":"ref8","article-title":"Parallel Programming Must Be Deterministic by Default","author":"bocchino","year":"2009","journal-title":"HotPar-1 First USENIX Workshop on Hot Topics in Parallelism"},{"key":"ref7","doi-asserted-by":"crossref","first-page":"97","DOI":"10.1145\/1639949.1640097","article-title":"A type and effect system for deterministic parallel Java","volume":"44","author":"bocchino","year":"2009","journal-title":"ACM SIGPLAN Notices"},{"key":"ref2","first-page":"85","article-title":"Serialization sets: a dynamic dependence-based parallel execution model","author":"allen","year":"2009","journal-title":"Proceedings of the 14th ACM SIGPLAN symposium on Principles and Practice of Parallel Programming"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/224056.224058"},{"year":"0","key":"ref1"},{"key":"ref20","doi-asserted-by":"crossref","first-page":"265","DOI":"10.1145\/1394608.1382144","article-title":"Rerun: Exploiting Episodes for Lightweight Race Recording","author":"hower","year":"2008","journal-title":"Proc 35th Intl Symposium on Computer Architecture ISCA'08"},{"key":"ref22","first-page":"1","article-title":"UltraSPARC IV Mirrors Predecessor","author":"krewell","year":"2003","journal-title":"MICROREPORT"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2005.35"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1145\/859618.859633"},{"key":"ref24","doi-asserted-by":"crossref","first-page":"92","DOI":"10.1145\/1105734.1105747","article-title":"Multifacet's General Execution-driven Multiprocessor Simulator (GEMS) Toolset","author":"martin","year":"2005","journal-title":"Computer Architecture News"},{"key":"ref41","first-page":"49","author":"xu","year":"0","journal-title":"A Regulated Transitive Reduction (RTR) for Longer Memory Race Recording"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1995.524548"},{"article-title":"Hvbrid Transactional Memory","year":"2006","author":"moir","key":"ref26"},{"key":"ref43","doi-asserted-by":"crossref","first-page":"325","DOI":"10.1145\/1555815.1555796","article-title":"A case for an interleaving constrained shared-memory multi-processor","volume":"37","author":"yu","year":"2009","journal-title":"SIGARCH Comput Archit News"},{"key":"ref25","article-title":"Virtualization without direct execution - designing a portable VM","author":"mihocka","year":"2008","journal-title":"The 1st Workshop on Architectural and Microarchitectural Support for Binary Translation"}],"event":{"name":"2011 IEEE 17th International Symposium on High Performance Computer Architecture (HPCA)","start":{"date-parts":[[2011,2,12]]},"location":"San Antonio, TX, USA","end":{"date-parts":[[2011,2,16]]}},"container-title":["2011 IEEE 17th International Symposium on High Performance Computer Architecture"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5743111\/5749710\/05749741.pdf?arnumber=5749741","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,6,9]],"date-time":"2019-06-09T23:48:11Z","timestamp":1560124091000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5749741\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,2]]},"references-count":43,"URL":"https:\/\/doi.org\/10.1109\/hpca.2011.5749741","relation":{},"subject":[],"published":{"date-parts":[[2011,2]]}}}