{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,23]],"date-time":"2024-10-23T06:30:40Z","timestamp":1729665040049,"version":"3.28.0"},"reference-count":28,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2011,2]]},"DOI":"10.1109\/hpca.2011.5749749","type":"proceedings-article","created":{"date-parts":[[2011,4,18]],"date-time":"2011-04-18T13:49:44Z","timestamp":1303134584000},"page":"431-442","source":"Crossref","is-referenced-by-count":7,"title":["Exploiting criticality to reduce bottlenecks in distributed uniprocessors"],"prefix":"10.1109","author":[{"given":"Behnam","family":"Robatmili","sequence":"first","affiliation":[]},{"given":"Sibi","family":"Govindan","sequence":"additional","affiliation":[]},{"given":"Doug","family":"Burger","sequence":"additional","affiliation":[]},{"given":"Stephen W.","family":"Keckler","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/605397.605420"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.41"},{"key":"ref12","doi-asserted-by":"crossref","first-page":"71","DOI":"10.1145\/545214.545224","article-title":"An instruction set and microarchitecture for instruction level distributed processing","author":"kim","year":"2002","journal-title":"International Symposium on Computer Architecture"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/12.795218"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1023\/A:1026479803767"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2003.1253185"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1992.696999"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1988.639255"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2006.1620788"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2008.4771776"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2001.903262"},{"key":"ref4","doi-asserted-by":"crossref","first-page":"83","DOI":"10.1145\/342001.339657","article-title":"Wattch: a framework for architectural-level power analysis and optimizations","volume":"28","author":"brooks","year":"2000","journal-title":"SIGArch Computer Architecture News"},{"journal-title":"Technical Report","year":"2006","author":"tarjan","key":"ref27"},{"key":"ref3","first-page":"529","article-title":"MJRTY - a fast majority vote algorithm","author":"boyer","year":"1977","journal-title":"Automated Reasoning Essays in Honor of Woody Bledsoe volume 1 of Automated Reasoning Series"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/1594233.1594332"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/384285.379253"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2008.209"},{"key":"ref7","first-page":"10","author":"govindan","year":"2010","journal-title":"Scaling power and performance via processor composability"},{"key":"ref2","doi-asserted-by":"crossref","first-page":"746","DOI":"10.1145\/1278480.1278667","article-title":"thousand core chipsa technology perspective","author":"borkar","year":"2007","journal-title":"2007 44th ACM\/IEEE Design Automation Conference DAC"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/1250662.1250686"},{"year":"0","key":"ref1"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1997.645805"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2003.1253204"},{"key":"ref21","first-page":"98","article-title":"RENO: a rename-based instruction optimizer","author":"rotenberg","year":"2005","journal-title":"International Symposium on Computer Architecture"},{"key":"ref24","first-page":"114","article-title":"Reducing power with dynamic critical path information","author":"seng","year":"2001","journal-title":"International Symposium on Microarchitecture"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1145\/859618.859667"},{"key":"ref26","doi-asserted-by":"crossref","first-page":"414","DOI":"10.1145\/223982.224451","article-title":"Multiscalar processors","author":"sohi","year":"1995","journal-title":"Proceedings 22nd Annual International Symposium on Computer Architecture ISCA"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2001.953283"}],"event":{"name":"2011 IEEE 17th International Symposium on High Performance Computer Architecture (HPCA)","start":{"date-parts":[[2011,2,12]]},"location":"San Antonio, TX, USA","end":{"date-parts":[[2011,2,16]]}},"container-title":["2011 IEEE 17th International Symposium on High Performance Computer Architecture"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5743111\/5749710\/05749749.pdf?arnumber=5749749","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,4,6]],"date-time":"2024-04-06T06:21:01Z","timestamp":1712384461000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5749749\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,2]]},"references-count":28,"URL":"https:\/\/doi.org\/10.1109\/hpca.2011.5749749","relation":{},"subject":[],"published":{"date-parts":[[2011,2]]}}}