{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,5]],"date-time":"2026-06-05T15:55:37Z","timestamp":1780674937838,"version":"3.54.1"},"reference-count":27,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2012,2]]},"DOI":"10.1109\/hpca.2012.6168944","type":"proceedings-article","created":{"date-parts":[[2012,3,26]],"date-time":"2012-03-26T21:53:22Z","timestamp":1332798802000},"page":"1-12","source":"Crossref","is-referenced-by-count":112,"title":["Balancing DRAM locality and parallelism in shared memory CMP systems"],"prefix":"10.1109","author":[{"given":"Min Kyu","family":"Jeong","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Doe Hyun","family":"Yoon","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Dam","family":"Sunwoo","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Mike","family":"Sullivan","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Ikhwan","family":"Lee","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Mattan","family":"Erez","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"19","article-title":"Effective management of DRAM bandwidth in multicore processors","author":"rafique","year":"0","journal-title":"Proc the 16th Int'l Conf on Parallel Architecture and Compilation Techniques (PAC) Sep 2007"},{"key":"17","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2008.7"},{"key":"18","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.24"},{"key":"15","doi-asserted-by":"publisher","DOI":"10.1145\/2155620.2155664"},{"key":"16","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.21"},{"key":"13","article-title":"Software-hardware cooperative DRAM bank partitioning for chip multiprocessors","author":"mi","year":"0","journal-title":"Proc the 2010 IFIP Int'l Conf Network and Parallel Computing (NPC) Sep 2010"},{"key":"14","year":"2011","journal-title":"Micron 2 Gb X4 X8 X16 DDR3 SDRAM MT41J512M4 MT41J256M4 and MT41J128M16"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2009.4919638"},{"key":"12","article-title":"Fully buffered DIMM (FB-DIMM) design considerations","author":"mctague","year":"2004","journal-title":"Intel Developer Forum"},{"key":"21","doi-asserted-by":"publisher","DOI":"10.1145\/378993.379244"},{"key":"20","first-page":"128","article-title":"Memory access scheduling","author":"rixner","year":"2000","journal-title":"Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat No RS00201) ISCA"},{"key":"22","year":"2006","journal-title":"SPEC CPU 2006"},{"key":"23","doi-asserted-by":"publisher","DOI":"10.1145\/1815961.1815983"},{"key":"24","article-title":"Improving power and data efficiency with threaded memory modules","author":"ware","year":"0","journal-title":"Proc Int'l Conf Computer Design (ICCD) Oct 2006"},{"key":"25","doi-asserted-by":"publisher","DOI":"10.1145\/2000064.2000100"},{"key":"26","doi-asserted-by":"crossref","DOI":"10.1109\/MICRO.2000.898056","article-title":"A permutation-based page interleaving scheme to reduce row-buffer conflicts and exploit data locality","author":"zhang","year":"0","journal-title":"Proc the 33rd Ann IEEE\/ACM Int'l Symp Microarchitecture (MICRO) Dec 2000"},{"key":"27","article-title":"Minirank: Adaptive DRAM architecture for improving memory power efficiency","author":"zheng","year":"0","journal-title":"Proc the 41st IEEE\/ACM Int'l Symp Microarchitecture (MICRO) Nov 2008"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/L-CA.2008.13"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1145\/1654059.1654102"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2010.51"},{"key":"1","year":"2007","journal-title":"Calculating Memory System Power for DDR3"},{"key":"7","author":"jeong","year":"0","journal-title":"DrSim A Platform for Flexible DRAM System Research"},{"key":"6","author":"hoelzle","year":"2009","journal-title":"The Datacenter as a Computer An Introduction to the Design of Warehouse-Scale Machines"},{"key":"5","article-title":"SimPoint 3.0: Faster and more flexible program analysis","author":"hamerly","year":"0","journal-title":"Proc the Workshop on Modeling Benchmarking and Simulation (MoBS) Jun 2005"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2010.36"},{"key":"9","article-title":"ATLAS: A scalable and high-performance scheduling algorithm for multiple memory controllers","author":"kim","year":"0","journal-title":"Proc the 16th Int'l Symp High-Performance Computer Architecture (HPCA) Jan 2010"},{"key":"8","article-title":"A day in the life of a data cache miss","author":"karkhanis","year":"0","journal-title":"Workshop on Memory Performance Issues 2002"}],"event":{"name":"2012 IEEE 18th International Symposium on High Performance Computer Architecture (HPCA)","location":"New Orleans, LA, USA","start":{"date-parts":[[2012,2,25]]},"end":{"date-parts":[[2012,2,29]]}},"container-title":["IEEE International Symposium on High-Performance Comp Architecture"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/6165554\/6168936\/06168944.pdf?arnumber=6168944","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,20]],"date-time":"2017-06-20T16:08:27Z","timestamp":1497974907000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6168944\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,2]]},"references-count":27,"URL":"https:\/\/doi.org\/10.1109\/hpca.2012.6168944","relation":{},"subject":[],"published":{"date-parts":[[2012,2]]}}}