{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,5,22]],"date-time":"2025-05-22T04:07:30Z","timestamp":1747886850903,"version":"3.41.0"},"reference-count":17,"publisher":"IEEE","license":[{"start":{"date-parts":[[2012,2,1]],"date-time":"2012-02-01T00:00:00Z","timestamp":1328054400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2012,2,1]],"date-time":"2012-02-01T00:00:00Z","timestamp":1328054400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2012,2]]},"DOI":"10.1109\/hpca.2012.6168951","type":"proceedings-article","created":{"date-parts":[[2012,3,26]],"date-time":"2012-03-26T21:53:22Z","timestamp":1332798802000},"page":"1-12","source":"Crossref","is-referenced-by-count":11,"title":["\u03c0-TM: Pessimistic invalidation for scalable lazy hardware transactional memory"],"prefix":"10.1109","author":[{"given":"Anurag","family":"Negi","sequence":"first","affiliation":[{"name":"Chalmers University of Technology, Sweden"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Rub\u00e9n","family":"Titos-Gil","sequence":"additional","affiliation":[{"name":"Universidad de Murcia, Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Manuel E.","family":"Acacio","sequence":"additional","affiliation":[{"name":"Universidad de Murcia, Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jos\u00e9 M.","family":"Garcia","sequence":"additional","affiliation":[{"name":"Universidad de Murcia, Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Per","family":"Stenstrom","sequence":"additional","affiliation":[{"name":"Chalmers University of Technology, Sweden"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/1250662.1250674"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC.2008.4636089"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2006.13"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2007.346189"},{"key":"ref5","article-title":"Predicting the scalability of an STM","volume-title":"TRANSACT\u2019 10: 5th ACM SIGPLAN Workshop on Transactional Computing","author":"Dragojevic","year":"2010"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2004.1310767"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1993.698569"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.2200\/S00070ED1V01Y200611CAC002"},{"key":"ref9","first-page":"48","article-title":"Dynamic self-invalidation: Reducing coherence overhead in shared-memory multiprocessors","volume-title":"Proceedings of the 22nd Int\u2019l Symp. on Computer Architecture","author":"Lebeck","year":"1995"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/2.982916"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/1105734.1105747"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ICSAMOS.2010.5642062"},{"key":"ref13","first-page":"144","article-title":"Scalable and reliable communication for hardware transactional memory","volume-title":"Proc. of the 17th Int\u2019l Conf. on Parallel Architectures and Compilation Techniques","author":"Pugsley","year":"2008"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2010.29"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2008.17"},{"key":"ref16","article-title":"EazyHTM: Eager-lazy hardware transactional memory","volume-title":"Proc. of the 42nd Int\u2019l Symp. on Microarchitecture","author":"Tomic","year":"2009"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2007.346204"}],"event":{"name":"2012 IEEE 18th International Symposium on High Performance Computer Architecture (HPCA)","start":{"date-parts":[[2012,2,25]]},"location":"New Orleans, LA, USA","end":{"date-parts":[[2012,2,29]]}},"container-title":["IEEE International Symposium on High-Performance Comp Architecture"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/6165554\/6168936\/06168951.pdf?arnumber=6168951","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,5,21]],"date-time":"2025-05-21T05:22:17Z","timestamp":1747804937000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/6168951\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,2]]},"references-count":17,"URL":"https:\/\/doi.org\/10.1109\/hpca.2012.6168951","relation":{},"subject":[],"published":{"date-parts":[[2012,2]]}}}