{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,8]],"date-time":"2026-01-08T05:26:14Z","timestamp":1767849974210,"version":"3.49.0"},"reference-count":44,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2013,2]]},"DOI":"10.1109\/hpca.2013.6522314","type":"proceedings-article","created":{"date-parts":[[2013,6,8]],"date-time":"2013-06-08T11:12:52Z","timestamp":1370689972000},"page":"143-154","source":"Crossref","is-referenced-by-count":66,"title":["Technology comparison for large last-level caches (L<sup>3<\/sup>Cs): Low-leakage SRAM, low write-energy STT-RAM, and refresh-optimized eDRAM"],"prefix":"10.1109","author":[{"family":"Mu-Tien Chang","sequence":"first","affiliation":[]},{"given":"P.","family":"Rosenfeld","sequence":"additional","affiliation":[]},{"family":"Shih-Lien Lu","sequence":"additional","affiliation":[]},{"given":"B.","family":"Jacob","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"19","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.2000.852812"},{"key":"35","article-title":"MARSSx86: A full system simulator for x86 cpus","author":"patel","year":"2011","journal-title":"DAC"},{"key":"17","doi-asserted-by":"crossref","first-page":"24","DOI":"10.1145\/1105734.1105739","article-title":"Exploring the cache design space for large scale cmps","volume":"33","author":"hsu","year":"2005","journal-title":"SIGARCH Comput Archit News"},{"key":"36","article-title":"A three transistor-cell, 1024-bit, 500ns mos ram","author":"regitz","year":"1970","journal-title":"ISSCC"},{"key":"18","article-title":"Timekeeping in the memory system: Predicting and optimizing memory behavior","author":"hu","year":"2002","journal-title":"ISCA"},{"key":"33","doi-asserted-by":"crossref","first-page":"82","DOI":"10.1145\/280756.280792","article-title":"Optimizing the DRAM refresh count for merged DRAM\/logic LSIs","author":"ohsawa","year":"1998","journal-title":"Proceedings 1998 International Symposium on Low Power Electronics and Design (IEEE Cat No 98TH8379) LPE"},{"key":"15","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2008.93"},{"key":"34","article-title":"Enhancement of data retention and write current scaling for sub-20nm stt-mram by utilizing dual interfaces for perpendicular magnetic anisotropy","author":"park","year":"2011","journal-title":"VLSI Technology"},{"key":"16","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.13"},{"key":"39","article-title":"Relaxing non-volatility for fast and energy-efficient stt-ram caches","author":"smullen","year":"2011","journal-title":"HPCA"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2012.2185930"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1109\/IMW.2011.5873205"},{"key":"37","doi-asserted-by":"publisher","DOI":"10.1109\/SOCC.2006.283903"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2128150"},{"key":"38","doi-asserted-by":"publisher","DOI":"10.1109\/L-CA.2011.4"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1088\/0953-8984\/19\/16\/165209"},{"key":"21","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2010.38"},{"key":"20","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228406"},{"key":"43","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2011.5937902"},{"key":"42","article-title":"PTLsim: A cycle accurate full system x86-64 microarchitectural simulator","author":"yourst","year":"2007","journal-title":"ISPASS"},{"key":"41","doi-asserted-by":"publisher","DOI":"10.1145\/1815961.1815973"},{"key":"40","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2007155"},{"key":"44","article-title":"Adaptive mode control: A static-power-efficient cache design","author":"zhou","year":"2001","journal-title":"PACT"},{"key":"22","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2010.97"},{"key":"23","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2001.937453"},{"key":"24","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2010.24"},{"key":"25","doi-asserted-by":"crossref","first-page":"1006","DOI":"10.1109\/TVLSI.2003.817524","article-title":"Block-based multiperiod dynamic memory design for low data-retention power","volume":"11","author":"kim","year":"2003","journal-title":"IEEE Trans VLSI"},{"key":"26","article-title":"Extended scalability of perpendicular sttmram towards sub-20nm mtj node","author":"kim","year":"2011","journal-title":"IEDM"},{"key":"27","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.848019"},{"key":"28","doi-asserted-by":"publisher","DOI":"10.1145\/339647.339669"},{"key":"29","doi-asserted-by":"publisher","DOI":"10.1109\/TMAG.2011.2159262"},{"key":"3","year":"0"},{"key":"2","year":"0"},{"key":"10","author":"bienia","year":"2011","journal-title":"Benchmarking Modern Multiprocessors"},{"key":"1","year":"0"},{"key":"30","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.40"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/ASSCC.2006.357915"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1145\/1061267.1061271"},{"key":"32","article-title":"RAIDR: Retention-aware intelligent dram refresh","author":"liu","year":"2012","journal-title":"ISCA"},{"key":"5","year":"0"},{"key":"31","doi-asserted-by":"publisher","DOI":"10.1109\/ISPDC.2009.14"},{"key":"4","year":"0"},{"key":"9","article-title":"QEMU, a fast and portable dynamic translator","author":"bellard","year":"2005","journal-title":"ATEC"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1145\/986537.986601"}],"event":{"name":"2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA)","location":"Shenzhen","start":{"date-parts":[[2013,2,23]]},"end":{"date-parts":[[2013,2,27]]}},"container-title":["2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6518038\/6522298\/06522314.pdf?arnumber=6522314","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,21]],"date-time":"2017-06-21T10:21:45Z","timestamp":1498040505000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6522314\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,2]]},"references-count":44,"URL":"https:\/\/doi.org\/10.1109\/hpca.2013.6522314","relation":{},"subject":[],"published":{"date-parts":[[2013,2]]}}}