{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,7]],"date-time":"2026-04-07T21:51:27Z","timestamp":1775598687858,"version":"3.50.1"},"reference-count":36,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2013,2]]},"DOI":"10.1109\/hpca.2013.6522334","type":"proceedings-article","created":{"date-parts":[[2013,6,8]],"date-time":"2013-06-08T15:12:52Z","timestamp":1370704372000},"page":"378-389","source":"Crossref","is-referenced-by-count":98,"title":["Breaking the on-chip latency barrier using SMART"],"prefix":"10.1109","author":[{"given":"T.","family":"Krishna","sequence":"first","affiliation":[]},{"given":"Chia-Hsin Owen","family":"Chen","sequence":"additional","affiliation":[]},{"family":"Woo Cheol Kwon","sequence":"additional","affiliation":[]},{"family":"Li-Shiuan Peh","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"19","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2011.2164538"},{"key":"35","doi-asserted-by":"publisher","DOI":"10.1109\/NOCS.2012.31"},{"key":"17","first-page":"51","author":"jain","year":"2010","journal-title":"Asynchronous Bypass Channels Improving Performance for Multisynchronous Nocs"},{"key":"36","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2007.4378780"},{"key":"18","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2011.40"},{"key":"33","author":"rabaey","year":"2002","journal-title":"Digital Integrated Circuits A Design Perspective"},{"key":"15","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2007.4378783"},{"key":"34","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2006.40"},{"key":"16","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2079450"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2009.4798251"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2011.108"},{"key":"11","author":"dally","year":"2003","journal-title":"Principles and Practices of Interconnection Networks"},{"key":"12","first-page":"401","article-title":"Kilo-NOC: A heterogeneous network-on-chip architecture for scalability and service guarantees","author":"grot","year":"2011","journal-title":"2011 38th Annual International Symposium on Computer Architecture (ISCA) ISCA"},{"key":"21","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2005.35"},{"key":"20","first-page":"552","article-title":"Equalized interconnects for onchip networks: Modeling and optimization framework","author":"kim","year":"2007","journal-title":"ICCAD"},{"key":"22","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.29"},{"key":"23","doi-asserted-by":"publisher","DOI":"10.1145\/2155620.2155630"},{"key":"24","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2009.64"},{"key":"25","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2010.5647666"},{"key":"26","first-page":"63","article-title":"A 4.6Tbits\/s 3.6GHz single-cycle NoC router with a novel switch allocator in 65nm CMOS","author":"kumar","year":"2007","journal-title":"ICCD"},{"key":"27","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2008.4771803"},{"key":"28","doi-asserted-by":"publisher","DOI":"10.1145\/1854273.1854332"},{"key":"29","author":"martin","year":"2005","journal-title":"Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset"},{"key":"3","year":"0"},{"key":"2","year":"0"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2005.36"},{"key":"1","year":"0"},{"key":"30","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2009.4798274"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2002.1044296"},{"key":"6","article-title":"Variability in architectural simulations of multi-threaded workloads","author":"alameldeen","year":"2003","journal-title":"HPCA"},{"key":"32","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228431"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2009.4919636"},{"key":"31","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2004.1310774"},{"key":"4","year":"0"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1145\/1454115.1454128"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1145\/1183401.1183430"}],"event":{"name":"2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA)","location":"Shenzhen","start":{"date-parts":[[2013,2,23]]},"end":{"date-parts":[[2013,2,27]]}},"container-title":["2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6518038\/6522298\/06522334.pdf?arnumber=6522334","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,23]],"date-time":"2017-03-23T02:35:33Z","timestamp":1490236533000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6522334\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,2]]},"references-count":36,"URL":"https:\/\/doi.org\/10.1109\/hpca.2013.6522334","relation":{},"subject":[],"published":{"date-parts":[[2013,2]]}}}