{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,8]],"date-time":"2024-09-08T04:34:04Z","timestamp":1725770044578},"reference-count":25,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2013,2]]},"DOI":"10.1109\/hpca.2013.6522336","type":"proceedings-article","created":{"date-parts":[[2013,6,8]],"date-time":"2013-06-08T15:12:52Z","timestamp":1370704372000},"page":"400-411","source":"Crossref","is-referenced-by-count":34,"title":["Refrint: Intelligent refresh to minimize power in on-chip multiprocessor cache hierarchies"],"prefix":"10.1109","author":[{"given":"A.","family":"Agrawal","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"P.","family":"Jain","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"A.","family":"Ansari","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"J.","family":"Torrellas","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"19","article-title":"An hybrid edr am\/sram macrocell to implement firstlevel data caches","author":"valero","year":"2009","journal-title":"International Symposium on Microarchitecture"},{"journal-title":"SESC Simulator","year":"2005","author":"renau","key":"17"},{"journal-title":"C ACTI 5 1 Technical Report","year":"2008","author":"thoziyoor","key":"18"},{"key":"15","doi-asserted-by":"publisher","DOI":"10.1145\/1062261.1062321"},{"key":"16","article-title":"GatedV dd: A circuit technique to reduce leakage in deep-submicron cache memories","author":"powell","year":"2000","journal-title":"International Symposium on Low Power Electronics and Design"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.40"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1147\/rd.491.0145"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2005.35"},{"journal-title":"International Symposium on Microarchitecture","article-title":"Framework for multicore and manycore architectures","year":"2009","key":"12"},{"key":"21","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2080611"},{"key":"20","doi-asserted-by":"crossref","DOI":"10.1109\/HPCA.2006.1598122","article-title":"Retention-aware placement in DR AM (R APID): Software methods for quasi-non-volatile DR AM","author":"venkatesan","year":"2006","journal-title":"International Symposium on High-Performance Computer Architecture"},{"key":"22","doi-asserted-by":"publisher","DOI":"10.1145\/1815961.1815973"},{"key":"23","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2001.903259"},{"key":"24","doi-asserted-by":"crossref","DOI":"10.1109\/HPCA.2002.995706","article-title":"Exploiting choice in resizable cache design to optimize deep-submicron processor energy-delay","author":"yang","year":"2002","journal-title":"Int Symposium on HighPerformance Computer Architecture"},{"key":"25","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2001.953288"},{"key":"3","article-title":"A 700MHz 2TlC embedded DRAM macro in a generic logic process with no boosted supplies","author":"chun","year":"2011","journal-title":"IEEE Int Solid-State Circuits Conf"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.908006"},{"key":"1","article-title":"A comprehensive memory modeling tool and its application t o the design and analysis of future memory hierarchies","author":"ahn","year":"2008","journal-title":"International Symposium on Computer Architecture"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2001.937453"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.13"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2002.1003572"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2008.93"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2009.2034764"},{"key":"9","article-title":"Embedded DRAM: Technology platform for the blue gene\/L chip","author":"lyer","year":"2005","journal-title":"IBM Journal 01 Research and Development"},{"key":"8","doi-asserted-by":"crossref","DOI":"10.1145\/566408.566423","article-title":"Managing leakage for transient data: Decay and quasistatic 4T memory cells","author":"hu","year":"2002","journal-title":"International Symposium on Low Power Electronics and Design"}],"event":{"name":"2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA)","start":{"date-parts":[[2013,2,23]]},"location":"Shenzhen","end":{"date-parts":[[2013,2,27]]}},"container-title":["2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6518038\/6522298\/06522336.pdf?arnumber=6522336","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,7,15]],"date-time":"2019-07-15T00:40:21Z","timestamp":1563151221000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6522336\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,2]]},"references-count":25,"URL":"https:\/\/doi.org\/10.1109\/hpca.2013.6522336","relation":{},"subject":[],"published":{"date-parts":[[2013,2]]}}}