{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,6]],"date-time":"2024-09-06T22:04:24Z","timestamp":1725660264166},"reference-count":45,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2013,2]]},"DOI":"10.1109\/hpca.2013.6522346","type":"proceedings-article","created":{"date-parts":[[2013,6,8]],"date-time":"2013-06-08T15:12:52Z","timestamp":1370704372000},"page":"520-531","source":"Crossref","is-referenced-by-count":3,"title":["In-network traffic regulation for Transactional Memory"],"prefix":"10.1109","author":[{"family":"Lihang Zhao","sequence":"first","affiliation":[]},{"family":"Woojin Choi","sequence":"additional","affiliation":[]},{"family":"Lizhong Chen","sequence":"additional","affiliation":[]},{"given":"J.","family":"Draper","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"19","doi-asserted-by":"crossref","DOI":"10.1007\/978-3-031-01725-4","author":"jerger","year":"2009","journal-title":"On-Chip Networks"},{"key":"35","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2005.54"},{"key":"17","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2006.15"},{"key":"36","doi-asserted-by":"publisher","DOI":"10.1145\/1323293.1294271"},{"key":"18","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2010.5416653"},{"key":"15","article-title":"The IBM blue gene\/Q compute chip","author":"haring","year":"2011","journal-title":"Micro IEEE"},{"key":"33","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2012.6168951"},{"key":"16","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1993.698569"},{"key":"34","doi-asserted-by":"publisher","DOI":"10.1145\/635506.605399"},{"key":"39","doi-asserted-by":"publisher","DOI":"10.1145\/1073814.1073861"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669150"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1145\/1815961.1815976"},{"key":"37","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2008.4658623"},{"year":"0","key":"11"},{"key":"38","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.24"},{"year":"0","key":"12"},{"key":"21","doi-asserted-by":"publisher","DOI":"10.1145\/605397.605420"},{"key":"20","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2008.4771777"},{"key":"43","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2007.346204"},{"key":"42","article-title":"ORION: A powerperformance simulator for interconnection networks","author":"wang","year":"2002","journal-title":"Procs of Int'l Symp on Microarchitecture"},{"key":"41","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2008.17"},{"key":"40","doi-asserted-by":"publisher","DOI":"10.1145\/1542275.1542299"},{"key":"45","article-title":"SELTM: Selective eager-lazy management for increased concurrency in transactional memory","author":"zhao","year":"2012","journal-title":"Proc Symp Parallel and Distributed Processing"},{"key":"44","doi-asserted-by":"publisher","DOI":"10.1145\/1378533.1378564"},{"key":"22","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555782"},{"key":"23","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2009.19"},{"key":"24","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2010.23"},{"key":"25","doi-asserted-by":"publisher","DOI":"10.1109\/2.982916"},{"key":"26","doi-asserted-by":"publisher","DOI":"10.1145\/859618.859642"},{"key":"27","first-page":"33","article-title":"Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset","author":"martin","year":"2005","journal-title":"SIGARCH Comput Archit News"},{"key":"28","doi-asserted-by":"publisher","DOI":"10.1145\/1250662.1250670"},{"key":"29","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC.2008.4636089"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1145\/1854273.1854293"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669143"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2009.4919636"},{"key":"10","doi-asserted-by":"crossref","DOI":"10.1145\/1028176.1006708","article-title":"Microarchitecture optimizations for exploiting memory-level parallelism","author":"chou","year":"2004","journal-title":"Proc Int l Symp Computer Architecture"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1145\/1250662.1250674"},{"key":"30","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2006.1598134"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1145\/1250662.1250667"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2011.5749718"},{"key":"32","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.33"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669133"},{"key":"31","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2001.903254"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2009.34"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2007.346189"}],"event":{"name":"2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA)","start":{"date-parts":[[2013,2,23]]},"location":"Shenzhen","end":{"date-parts":[[2013,2,27]]}},"container-title":["2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6518038\/6522298\/06522346.pdf?arnumber=6522346","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,7,2]],"date-time":"2023-07-02T08:27:53Z","timestamp":1688286473000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6522346\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,2]]},"references-count":45,"URL":"https:\/\/doi.org\/10.1109\/hpca.2013.6522346","relation":{},"subject":[],"published":{"date-parts":[[2013,2]]}}}