{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,5]],"date-time":"2025-10-05T04:34:21Z","timestamp":1759638861293,"version":"3.28.0"},"reference-count":34,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2014,2]]},"DOI":"10.1109\/hpca.2014.6835940","type":"proceedings-article","created":{"date-parts":[[2014,7,28]],"date-time":"2014-07-28T18:48:01Z","timestamp":1406573281000},"page":"296-307","source":"Crossref","is-referenced-by-count":37,"title":["MP3: Minimizing performance penalty for power-gating of Clos network-on-chip"],"prefix":"10.1109","author":[{"given":"Lizhong","family":"Chen","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Lihang","family":"Zhao","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ruisheng","family":"Wang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Timothy M.","family":"Pinkston","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"19","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.29"},{"key":"17","doi-asserted-by":"publisher","DOI":"10.1109\/LPE.2003.1231952"},{"key":"18","doi-asserted-by":"publisher","DOI":"10.1145\/1065579.1065726"},{"key":"33","first-page":"1","article-title":"Floorplan optimization of fat-tree based networks-on-chip for chip multiprocessors","volume":"pp","author":"wang","year":"2012","journal-title":"IEEE Transactions on Computers"},{"key":"15","doi-asserted-by":"publisher","DOI":"10.1109\/HOTI.2009.13"},{"key":"34","doi-asserted-by":"publisher","DOI":"10.1109\/NEWCAS.2010.5603776"},{"key":"16","first-page":"181","article-title":"Design of highradix clos network-on-chip","author":"kao","year":"2010","journal-title":"4th International Symposium on Networks on Chip (NOCS)"},{"key":"13","first-page":"559","article-title":"Benefits and costs of power-gating technique","author":"jiang","year":"2005","journal-title":"International Conference on Computer Design (ICCD)"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1109\/NOCS.2009.5071460"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/LPE.2004.1349303"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2010.48"},{"key":"21","doi-asserted-by":"publisher","DOI":"10.1145\/1594233.1594331"},{"key":"20","first-page":"91","article-title":"Dynamic voltage scaling with links for power optimization of interconnection networks","author":"li","year":"2003","journal-title":"11th International Symposium on High-Performance Computer Architecture (HPCA)"},{"key":"22","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2011.5749737"},{"key":"23","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2008.4484015"},{"key":"24","doi-asserted-by":"publisher","DOI":"10.1109\/NOCS.2008.4492722"},{"key":"25","doi-asserted-by":"publisher","DOI":"10.1109\/NOCS.2010.16"},{"key":"26","first-page":"1","article-title":"Niagara 2 opens the floodgates","volume":"20","author":"mcghan","year":"2006","journal-title":"Microprocessor Report"},{"key":"27","first-page":"12","article-title":"ViChaR: A dynamic virtual channel regulator for network-on-chip routers","author":"nicopoulos","year":"2006","journal-title":"35th International Symposium on Microarchitecture (MICRO)"},{"key":"28","first-page":"362","article-title":"Layout, performance and power trade-offs in mesh- based network-on-chip architectures","author":"pamunuwa","year":"2003","journal-title":"VLSI-SoC"},{"key":"29","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2013.6522345"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1145\/1183401.1183430"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2009.4919636"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2079450"},{"year":"2013","key":"1"},{"key":"30","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2006.40"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1145\/2485922.2485950"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1002\/j.1538-7305.1953.tb01433.x"},{"key":"32","doi-asserted-by":"publisher","DOI":"10.1109\/NOCS.2012.31"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2012.33"},{"key":"31","first-page":"510","article-title":"Design-space exploration of poweraware on\/off interconnection networks","author":"soteriou","year":"2004","journal-title":"2nd International Conference on Computer Design (ICCD)"},{"key":"4","article-title":"Parsec 2.0: A new benchmark suite for chipmultiprocessors","author":"bienia","year":"2009","journal-title":"Proceedings of the 5th Annual Workshop on Modeling Benchmarking and Simulation"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2007.4378783"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669144"}],"event":{"name":"2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA)","start":{"date-parts":[[2014,2,15]]},"location":"Orlando, FL, USA","end":{"date-parts":[[2014,2,19]]}},"container-title":["2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6823235\/6835920\/06835940.pdf?arnumber=6835940","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,23]],"date-time":"2017-03-23T19:53:21Z","timestamp":1490298801000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6835940\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,2]]},"references-count":34,"URL":"https:\/\/doi.org\/10.1109\/hpca.2014.6835940","relation":{},"subject":[],"published":{"date-parts":[[2014,2]]}}}