{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,7]],"date-time":"2024-09-07T01:30:26Z","timestamp":1725672626392},"reference-count":33,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2014,2]]},"DOI":"10.1109\/hpca.2014.6835950","type":"proceedings-article","created":{"date-parts":[[2014,7,28]],"date-time":"2014-07-28T18:48:01Z","timestamp":1406573281000},"page":"404-415","source":"Crossref","is-referenced-by-count":12,"title":["Atomic SC for simple in-order processors"],"prefix":"10.1109","author":[{"given":"Dibakar","family":"Gope","sequence":"first","affiliation":[]},{"given":"Mikko H.","family":"Lipasti","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"19","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555785"},{"key":"17","article-title":"WeeFence: Toward making fences free in TSO","author":"duan","year":"2013","journal-title":"ISCA"},{"key":"18","article-title":"Improving the throughput of synchronization by insertion of delays","author":"rajwar","year":"2000","journal-title":"HPCA"},{"year":"0","key":"33"},{"key":"15","doi-asserted-by":"publisher","DOI":"10.1145\/2150976.2151006"},{"key":"16","doi-asserted-by":"publisher","DOI":"10.1145\/1854273.1854312"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1145\/378580.378604"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1991.1021604"},{"key":"11","article-title":"Memory ordering: A value-based approach","author":"cain","year":"2004","journal-title":"ISCA"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2004.1310767"},{"key":"21","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2009.30"},{"key":"20","article-title":"Implementing sequential consistency in cache-based systems","author":"adve","year":"1990","journal-title":"ICPP"},{"key":"22","article-title":"Accelerating atomic operations on the GPU for broader applicability","author":"franey","year":"2013","journal-title":"NoCS"},{"key":"23","doi-asserted-by":"publisher","DOI":"10.1145\/1993498.1993522"},{"key":"24","article-title":"End-to-end SC","author":"singh","year":"2011","journal-title":"ISCA"},{"year":"0","key":"25"},{"year":"0","key":"26"},{"key":"27","doi-asserted-by":"publisher","DOI":"10.1145\/1454115.1454128"},{"key":"28","article-title":"Pitfalls of ORION-Based simulation","author":"hayenga","year":"2012","journal-title":"WDDD"},{"year":"0","key":"29"},{"key":"3","article-title":"Two techniques to enhance the performance of memory consistency models","author":"gharachorloo","year":"1991","journal-title":"ISCA"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/2.546611"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1145\/1250662.1250696"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1979.1675439"},{"key":"30","doi-asserted-by":"publisher","DOI":"10.1145\/30350.30377"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1145\/307338.300993"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2002.1106016"},{"key":"32","doi-asserted-by":"publisher","DOI":"10.1145\/2485922.2485940"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1145\/1250662.1250697"},{"key":"31","doi-asserted-by":"crossref","first-page":"48","DOI":"10.1109\/ISCA.1995.524548","article-title":"Dynamic self-invalidation: reducing coherence overhead in shared-memory multiprocessors","author":"lebeck","year":"1995","journal-title":"Proceedings 22nd Annual International Symposium on Computer Architecture ISCA"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1990.134502"},{"key":"9","doi-asserted-by":"crossref","DOI":"10.1145\/258492.258512","article-title":"Using speculative retirement and larger instruction windows to narrow the performance gap between memory consistency models","author":"ranganathan","year":"1997","journal-title":"SPAA"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/2.707614"}],"event":{"name":"2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA)","start":{"date-parts":[[2014,2,15]]},"location":"Orlando, FL, USA","end":{"date-parts":[[2014,2,19]]}},"container-title":["2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6823235\/6835920\/06835950.pdf?arnumber=6835950","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,7,15]],"date-time":"2023-07-15T14:50:55Z","timestamp":1689432655000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6835950\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,2]]},"references-count":33,"URL":"https:\/\/doi.org\/10.1109\/hpca.2014.6835950","relation":{},"subject":[],"published":{"date-parts":[[2014,2]]}}}