{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,18]],"date-time":"2025-11-18T11:48:34Z","timestamp":1763466514719,"version":"3.28.0"},"reference-count":51,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2014,2]]},"DOI":"10.1109\/hpca.2014.6835953","type":"proceedings-article","created":{"date-parts":[[2014,7,28]],"date-time":"2014-07-28T18:48:01Z","timestamp":1406573281000},"page":"440-451","source":"Crossref","is-referenced-by-count":18,"title":["Tangle: Route-oriented dynamic voltage minimization for variation-afflicted, energy-efficient on-chip networks"],"prefix":"10.1109","author":[{"given":"Amin","family":"Ansari","sequence":"first","affiliation":[]},{"given":"Asit","family":"Mishra","sequence":"additional","affiliation":[]},{"given":"Jianping","family":"Xu","sequence":"additional","affiliation":[]},{"given":"Josep","family":"Torrellas","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"35","doi-asserted-by":"publisher","DOI":"10.1109\/2.917539"},{"key":"36","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2005.104"},{"key":"33","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669151"},{"key":"34","doi-asserted-by":"publisher","DOI":"10.1145\/2000064.2000111"},{"key":"39","doi-asserted-by":"publisher","DOI":"10.1145\/1391469.1391627"},{"key":"37","doi-asserted-by":"publisher","DOI":"10.1109\/TDSC.2008.59"},{"key":"38","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2006.157"},{"key":"43","doi-asserted-by":"publisher","DOI":"10.1145\/605397.605403"},{"key":"42","doi-asserted-by":"publisher","DOI":"10.1109\/TSM.2007.913186"},{"key":"41","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2001.903268"},{"key":"40","first-page":"93","article-title":"Exploring fault-tolerant network-on-chip architectures","author":"park","year":"2006","journal-title":"DSN"},{"key":"22","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.19"},{"key":"23","doi-asserted-by":"publisher","DOI":"10.1145\/1095890.1095915"},{"key":"24","first-page":"123","article-title":"System level analysis of fast, per-core DVFS using on-chip switching regulators","author":"kim","year":"2008","journal-title":"HPCA"},{"key":"25","first-page":"241","article-title":"IDEAL: Inter-router dual-function energy and area-efficient links for network-on-chip (NoC) architectures","author":"kodi","year":"2008","journal-title":"ISCA"},{"key":"26","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2004.1311885"},{"key":"27","doi-asserted-by":"publisher","DOI":"10.1145\/1785481.1785568"},{"key":"28","first-page":"63","article-title":"A 4.6Tbits\/s 3.6GHz single-cycle NoC router with a novel switch allocator in 65nm CMOS","author":"kumar","year":"2007","journal-title":"ICCD"},{"key":"29","doi-asserted-by":"publisher","DOI":"10.1109\/NOCS.2008.4492731"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2005.110"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/40.782564"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2002.998256"},{"key":"7","article-title":"A fully-integrated switched-capacitor 2:1 voltage converter with regulation capability and 90% efficiency at 2.3a\/mm2","author":"chang","year":"2010","journal-title":"Symposium on VLSI Circuits"},{"key":"30","first-page":"504","article-title":"Mitigating the impact of process variations on processor register files and execution units","author":"liang","year":"2006","journal-title":"Micro"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2013.6522319"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1016\/S0019-9958(60)90287-4"},{"key":"32","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2009.13"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1145\/1811100.1811101"},{"key":"31","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2008.12"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2003.1195021"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2080550"},{"journal-title":"2012 Update","year":"0","key":"19"},{"key":"17","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2079450"},{"key":"18","doi-asserted-by":"publisher","DOI":"10.1147\/rd.144.0390"},{"key":"15","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2009.4798256"},{"key":"16","article-title":"Pitfalls of ORION-based simulation","author":"hayenga","year":"2012","journal-title":"WDDD"},{"key":"13","first-page":"111","article-title":"Architecting reliable multi-core networkon- chip for small scale processing technology","author":"fu","year":"2010","journal-title":"DSN"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228372"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1145\/2150976.2151008"},{"key":"12","doi-asserted-by":"crossref","first-page":"812","DOI":"10.1145\/1629911.1630119","article-title":"vicis: a reliable network for unreliable silicon","author":"fick","year":"2009","journal-title":"2009 46th ACM\/IEEE Design Automation Conference dac"},{"key":"21","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2012.6263951"},{"key":"20","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2003.821548"},{"key":"49","first-page":"294","article-title":"Orion: A powerperformance simulator for interconnection networks","volume":"35","author":"wang","year":"2002","journal-title":"Micro"},{"key":"48","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2008.4771785"},{"key":"45","first-page":"103","article-title":"Coding for systern-on-chip networks: a unified framework","author":"sridhara","year":"2004","journal-title":"Proceedings 41st Design Automation Conference 2004 DAC"},{"key":"44","doi-asserted-by":"publisher","DOI":"10.1145\/1403375.1403715"},{"key":"47","doi-asserted-by":"publisher","DOI":"10.1145\/1250662.1250703"},{"key":"46","doi-asserted-by":"publisher","DOI":"10.1109\/NOCS.2012.31"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2003.1253179"},{"key":"51","doi-asserted-by":"publisher","DOI":"10.1145\/1815961.1815973"},{"key":"50","doi-asserted-by":"crossref","first-page":"364","DOI":"10.1145\/1278480.1278573","article-title":"The Impact of NBTI on the Performance of Combinational and Sequential Circuits","author":"wenping wang","year":"2007","journal-title":"2007 44th ACM\/IEEE Design Automation Conference DAC"}],"event":{"name":"2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA)","start":{"date-parts":[[2014,2,15]]},"location":"Orlando, FL, USA","end":{"date-parts":[[2014,2,19]]}},"container-title":["2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6823235\/6835920\/06835953.pdf?arnumber=6835953","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,22]],"date-time":"2017-06-22T17:25:44Z","timestamp":1498152344000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6835953\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,2]]},"references-count":51,"URL":"https:\/\/doi.org\/10.1109\/hpca.2014.6835953","relation":{},"subject":[],"published":{"date-parts":[[2014,2]]}}}