{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,29]],"date-time":"2026-03-29T02:27:34Z","timestamp":1774751254264,"version":"3.50.1"},"reference-count":38,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2014,2]]},"DOI":"10.1109\/hpca.2014.6835954","type":"proceedings-article","created":{"date-parts":[[2014,7,28]],"date-time":"2014-07-28T18:48:01Z","timestamp":1406573281000},"page":"452-463","source":"Crossref","is-referenced-by-count":29,"title":["Improving cache performance using read-write partitioning"],"prefix":"10.1109","author":[{"given":"Samira","family":"Khan","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Alaa R.","family":"Alameldeen","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Chris","family":"Wilkerson","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Onur","family":"Mutluy","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Daniel A.","family":"Jimenezz","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"19","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669139"},{"key":"17","article-title":"DRAM-aware last-level cache writeback: Reducing write-caused interference in memory systems","author":"lee","year":"2010","journal-title":"Technical Report TR-HPS-2010-002"},{"key":"35","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2012.6237027"},{"key":"18","doi-asserted-by":"crossref","DOI":"10.1145\/360128.360132","article-title":"Eager writeback - A technique for improving bandwidth utilization","author":"lee","year":"2000","journal-title":"Micro"},{"key":"36","doi-asserted-by":"publisher","DOI":"10.1145\/2155620.2155671"},{"key":"33","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2010.102"},{"key":"15","doi-asserted-by":"publisher","DOI":"10.1145\/339647.339669"},{"key":"34","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1995.476816"},{"key":"16","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555758"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2013.6557176"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1145\/379240.379259"},{"key":"37","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555778"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2012.6169030"},{"key":"38","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555759"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2007.70816"},{"key":"21","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2011.5749733"},{"key":"20","doi-asserted-by":"publisher","DOI":"10.1145\/1065010.1065034"},{"key":"22","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2012.6237037"},{"key":"23","article-title":"ARC: A self-tuning, low overhead replacement cache","author":"megiddo","year":"2003","journal-title":"FAST"},{"key":"24","doi-asserted-by":"publisher","DOI":"10.1145\/781027.781076"},{"key":"25","article-title":"Exploiting single-usage for effective memory management","author":"piquet","year":"2007","journal-title":"ACSAC"},{"key":"26","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2006.5"},{"key":"27","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.49"},{"key":"28","doi-asserted-by":"publisher","DOI":"10.1145\/1250662.1250709"},{"key":"29","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555760"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/L-CA.2004.4"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669164"},{"key":"1","article-title":"CAR: Clock with adaptive replacement","author":"bansal","year":"2004","journal-title":"FAST"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2010.24"},{"key":"30","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2010.5416645"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2003.1183550"},{"key":"6","article-title":"High performance cache replacement using rereference interval prediction","author":"jaleel","year":"2010","journal-title":"ISCA"},{"key":"32","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2001.937442"},{"key":"5","article-title":"CMPim: A pin-based on-the-fly single\/multicore cache simulator","author":"jaleel","year":"2008","journal-title":"MOBS"},{"key":"4","author":"jaleel","year":"0","journal-title":"1st JILP Workshop on Computer Architecture Competitions (JWAC-1) Cache Replacement Championship"},{"key":"31","doi-asserted-by":"publisher","DOI":"10.1145\/2370816.2370868"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2007.4601909"},{"key":"8","article-title":"2Q: A low overhead high performance buffer management replacement algorithm","author":"johnson","year":"1994","journal-title":"VLDB"}],"event":{"name":"2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA)","location":"Orlando, FL, USA","start":{"date-parts":[[2014,2,15]]},"end":{"date-parts":[[2014,2,19]]}},"container-title":["2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6823235\/6835920\/06835954.pdf?arnumber=6835954","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,7,15]],"date-time":"2023-07-15T14:49:52Z","timestamp":1689432592000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6835954\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,2]]},"references-count":38,"URL":"https:\/\/doi.org\/10.1109\/hpca.2014.6835954","relation":{},"subject":[],"published":{"date-parts":[[2014,2]]}}}