{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,25]],"date-time":"2026-02-25T17:45:01Z","timestamp":1772041501676,"version":"3.50.1"},"reference-count":45,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2014,2]]},"DOI":"10.1109\/hpca.2014.6835976","type":"proceedings-article","created":{"date-parts":[[2014,7,28]],"date-time":"2014-07-28T18:48:01Z","timestamp":1406573281000},"page":"60-71","source":"Crossref","is-referenced-by-count":14,"title":["Understanding the impact of gate-level physical reliability effects on whole program execution"],"prefix":"10.1109","author":[{"given":"Raghuraman","family":"Balasubramanian","sequence":"first","affiliation":[]},{"given":"Karthikeyan","family":"Sankaralingam","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"19","doi-asserted-by":"publisher","DOI":"10.1109\/32.815322"},{"key":"35","doi-asserted-by":"publisher","DOI":"10.1016\/j.microrel.2006.10.006"},{"key":"17","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2011.5763096"},{"key":"36","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2007.23"},{"key":"18","doi-asserted-by":"publisher","DOI":"10.1145\/859618.859631"},{"key":"33","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2005.104"},{"key":"15","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2013.6657044"},{"key":"34","doi-asserted-by":"publisher","DOI":"10.1145\/1993498.1993518"},{"key":"16","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2011.5763258"},{"key":"39","doi-asserted-by":"publisher","DOI":"10.1109\/FTCS.1997.614074"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2003.1253179"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1145\/2150976.2151008"},{"key":"37","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2002.1028924"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.34"},{"key":"38","doi-asserted-by":"publisher","DOI":"10.1145\/1168857.1168868"},{"key":"12","article-title":"Relax: An architectural framework for software recovery of hardware faults","author":"de kruijf","year":"0","journal-title":"ISCA '10"},{"key":"21","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2009.4798242"},{"key":"20","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2007.100"},{"key":"43","doi-asserted-by":"publisher","DOI":"10.1109\/ICSICT.2010.5667399"},{"key":"42","first-page":"112","article-title":"Tunable replica circuits and adaptive voltage-frequency techniques for dynamic voltage, temperature, and aging variation tolerance","author":"tschanz","year":"2009","journal-title":"Symposium on VLSI Circuits"},{"key":"41","article-title":"Safetynet: Improving the availability of shared memory multiprocessors with global checkpoint\/recovery","author":"sorin","year":"0","journal-title":"ISCA '02"},{"key":"40","article-title":"Detecting emerging wearout faults","author":"smolens","year":"0","journal-title":"SELSE '07"},{"key":"45","article-title":"Wearmon: Reliability monitoring using adaptive critical path testing","author":"zandian","year":"0","journal-title":"DSN '12"},{"key":"44","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2012.6401593"},{"key":"22","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2007.346196"},{"key":"23","article-title":"Exploiting soft computing for increased fault tolerance","author":"li","year":"2006","journal-title":"Workshop on Architectural Support for Gigascale Integration"},{"key":"24","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.18"},{"key":"25","doi-asserted-by":"publisher","DOI":"10.1109\/101.340310"},{"key":"26","article-title":"Detailed design and evaluation of redundant multithreading alternatives","author":"mukherjee","year":"0","journal-title":"ISCA '02"},{"key":"27","doi-asserted-by":"publisher","DOI":"10.1145\/2000064.2000089"},{"key":"28","year":"0"},{"key":"29","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2012.6231069"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2007.22"},{"key":"2","year":"0"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1145\/2000064.2000067"},{"key":"1","year":"0"},{"key":"30","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2008.4751886"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1145\/1629911.1629915"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.35"},{"key":"32","article-title":"Revive: Costeffective architectural support for rollback recovery in shared-memory multiprocessors","author":"prvulovic","year":"0","journal-title":"ISCA '02"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1145\/2540708.2540720"},{"key":"31","doi-asserted-by":"publisher","DOI":"10.1109\/TDSC.2010.26"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1999.809458"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1145\/2463209.2488859"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/12.544481"}],"event":{"name":"2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA)","location":"Orlando, FL, USA","start":{"date-parts":[[2014,2,15]]},"end":{"date-parts":[[2014,2,19]]}},"container-title":["2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6823235\/6835920\/06835976.pdf?arnumber=6835976","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,23]],"date-time":"2017-03-23T23:35:41Z","timestamp":1490312141000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6835976\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,2]]},"references-count":45,"URL":"https:\/\/doi.org\/10.1109\/hpca.2014.6835976","relation":{},"subject":[],"published":{"date-parts":[[2014,2]]}}}