{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,8,23]],"date-time":"2025-08-23T05:11:50Z","timestamp":1755925910829,"version":"3.28.0"},"reference-count":38,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2015,2]]},"DOI":"10.1109\/hpca.2015.7056018","type":"proceedings-article","created":{"date-parts":[[2015,3,10]],"date-time":"2015-03-10T18:13:51Z","timestamp":1426011231000},"page":"13-25","source":"Crossref","is-referenced-by-count":28,"title":["BeBoP: A cost effective predictor infrastructure for superscalar value prediction"],"prefix":"10.1109","author":[{"given":"Arthur","family":"Perais","sequence":"first","affiliation":[]},{"given":"Andre","family":"Seznec","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"journal-title":"CPU2006","year":"0","key":"ref38"},{"key":"ref33","article-title":"Implementations of context based value predictors","author":"sazeides","year":"1998","journal-title":"Tech Rep ECE97-8"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1997.645815"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-47847-7_11"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1145\/335231.335250"},{"journal-title":"CPU2000","year":"0","key":"ref37"},{"key":"ref36","first-page":"1","article-title":"A case for (partially) TAgged GEometric history length branch prediction","volume":"8","author":"seznec","year":"2006","journal-title":"Journal of Instruction Level Parallelism"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2002.1003587"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1145\/2155620.2155635"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1998.694787"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/290409.290411"},{"key":"ref12","article-title":"The Intel Pentium M processor: Microarchitecture and performance","volume":"7","author":"gochman","year":"2003","journal-title":"Intel Technology Journal"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2001.903264"},{"key":"ref14","first-page":"80","article-title":"40-entry unified out-of-order scheduler and integer execution unit for the AMD Bulldozer x86_64 core","author":"golden","year":"0"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1998.742783"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/859622.859623"},{"key":"ref17","first-page":"231","article-title":"Decoupled value prediction on trace processors","author":"lee","year":"2000","journal-title":"Proceedings of the International Symposium on High-Performance Computer Architecture"},{"key":"ref18","doi-asserted-by":"crossref","first-page":"847","DOI":"10.1109\/12.947012","article-title":"on table bandwidth and its update delay for value prediction on wide-issue ilp processors","volume":"50","author":"lee","year":"2001","journal-title":"IEEE Transactions on Computers"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1996.566464"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2005.43"},{"journal-title":"Improving context-based load value prediction","year":"2000","author":"burtscher","key":"ref4"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2003.1238020"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/2024716.2024718"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1998.694770"},{"journal-title":"Efficient and accurate value prediction using dynamic classification","year":"1998","author":"rychlik","key":"ref29"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2000.878272"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2002.1003560"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1147\/rd.374.0547"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/514191.514201"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2005.19"},{"key":"ref1","first-page":"11","article-title":"AMD K6-III Processor Data Sheet","year":"1998","journal-title":"Advanced Micro Devices"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/237090.237173"},{"key":"ref22","article-title":"Speculative execution based on value prediction","author":"mendelson","year":"1997","journal-title":"Technical Report Technion - Israel Institute of Technology"},{"key":"ref21","article-title":"Width prediction for reducing value predictor size and power","author":"loh","year":"2003","journal-title":"First Value Prediction Workshop ISCA"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1997.604689"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.1999.744311"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2014.6835952"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1145\/2678373.2665742"}],"event":{"name":"2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA)","start":{"date-parts":[[2015,2,7]]},"location":"Burlingame, CA, USA","end":{"date-parts":[[2015,2,11]]}},"container-title":["2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7048058\/7056013\/07056018.pdf?arnumber=7056018","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,23]],"date-time":"2017-06-23T03:04:00Z","timestamp":1498187040000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7056018\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,2]]},"references-count":38,"URL":"https:\/\/doi.org\/10.1109\/hpca.2015.7056018","relation":{},"subject":[],"published":{"date-parts":[[2015,2]]}}}