{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,21]],"date-time":"2026-02-21T19:48:32Z","timestamp":1771703312143,"version":"3.50.1"},"reference-count":46,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2015,2]]},"DOI":"10.1109\/hpca.2015.7056023","type":"proceedings-article","created":{"date-parts":[[2015,3,10]],"date-time":"2015-03-10T18:13:51Z","timestamp":1426011231000},"page":"76-88","source":"Crossref","is-referenced-by-count":102,"title":["Coordinated static and dynamic cache bypassing for GPUs"],"prefix":"10.1109","author":[{"given":"Xiaolong","family":"Xie","sequence":"first","affiliation":[]},{"given":"Yun","family":"Liang","sequence":"additional","affiliation":[]},{"given":"Yu","family":"Wang","sequence":"additional","affiliation":[]},{"given":"Guangyu","family":"Sun","sequence":"additional","affiliation":[]},{"given":"Tao","family":"Wang","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2012.16"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1145\/2485922.2485953"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2013.2278025"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1145\/1815961.1815992"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2008.4771793"},{"key":"ref30","article-title":"Real-time implementation and performance optimization of 3D sound localization on GPUs","author":"liang","year":"0","journal-title":"Proceedings Design Automation and Test in Europe Conference and Exhibition DATE"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2012.17"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1145\/2451116.2451160"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2014.6835955"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1145\/2155620.2155656"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.30"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1145\/2540708.2540718"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/2000064.2000075"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/2000064.2000093"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/2155620.2155675"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2012.18"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/InPar.2012.6339595"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/1454115.1454152"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555775"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/2304576.2304582"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2014.6835938"},{"key":"ref28","doi-asserted-by":"crossref","first-page":"461","DOI":"10.1109\/ASPDAC.2013.6509639","article-title":"Register and thread structure optimization for GPUs","author":"liang","year":"2013","journal-title":"Proceedings of the 18th Asia and South Pacific Design Automation Conference (ASP-DAC)"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2009.4919648"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2010.44"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/1693453.1693470"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/2613908.2613909"},{"key":"ref29","article-title":"Efficient GPU spatial-temporal multitasking","author":"liang","year":"2014","journal-title":"IEEE Transactions on Parallel and Distributed Systems"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC.2009.5306797"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2012.43"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2012.18"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2012.6168946"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2011.5749714"},{"key":"ref1","article-title":"NVIDIA","year":"0","journal-title":"Occupancy Calculator"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2013.6691165"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/2451116.2451158"},{"key":"ref45","first-page":"134","article-title":"Compiler managed micro-cache bypassing for high performance EPIC processors","author":"wu","year":"2002","journal-title":"MICRO 35 Proceedings of the 35th Annual ACM\/IEEE International Symposium on Microarchitecture"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1997.604734"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1145\/2485922.2485951"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1109\/InPar.2012.6339606"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2010.24"},{"key":"ref41","article-title":"The IMPACT Research Group, Parboil Benchmark Suite","author":"stratton","year":"0"},{"key":"ref23","first-page":"157","article-title":"Neither more nor less: Optimizing thread-level parallelism for GPGPUs","author":"kayiran","year":"2013","journal-title":"Proceedings International Conference on Parallel Architectures and Compilation Techniques PACT"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1145\/2155620.2155671"},{"key":"ref26","doi-asserted-by":"crossref","first-page":"144","DOI":"10.1145\/384285.379259","article-title":"Dead-block prediction & dead-block correlating prefetchers","author":"lai","year":"2001","journal-title":"Proceedings 28th Annual International Symposium on Computer Architecture ISCA-01"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1995.476816"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2007.70816"}],"event":{"name":"2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA)","location":"Burlingame, CA, USA","start":{"date-parts":[[2015,2,7]]},"end":{"date-parts":[[2015,2,11]]}},"container-title":["2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7048058\/7056013\/07056023.pdf?arnumber=7056023","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,5,1]],"date-time":"2022-05-01T17:44:02Z","timestamp":1651427042000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7056023\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,2]]},"references-count":46,"URL":"https:\/\/doi.org\/10.1109\/hpca.2015.7056023","relation":{},"subject":[],"published":{"date-parts":[[2015,2]]}}}