{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,2]],"date-time":"2026-07-02T15:48:38Z","timestamp":1783007318701,"version":"3.54.5"},"reference-count":32,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2015,2]]},"DOI":"10.1109\/hpca.2015.7056024","type":"proceedings-article","created":{"date-parts":[[2015,3,10]],"date-time":"2015-03-10T18:13:51Z","timestamp":1426011231000},"page":"89-100","source":"Crossref","is-referenced-by-count":57,"title":["Priority-based cache allocation in throughput processors"],"prefix":"10.1109","author":[{"given":"Dong","family":"Li","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Minsoo","family":"Rhu","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Daniel R.","family":"Johnson","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Mike","family":"O'Connor","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Mattan","family":"Erez","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Doug","family":"Burger","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Donald S.","family":"Fussell","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Stephen W.","family":"Redder","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1145\/2540708.2540717"},{"key":"ref31","article-title":"ATI Stream Computing OpenCL Programming Guide","year":"2010"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1145\/263580.263599"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/2304576.2304582"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2010.83"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2010.38"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2080491"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2010.5647747"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/2155620.2155656"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/2000064.2000093"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2014.6835938"},{"key":"ref18","article-title":"CUDA C\/C++ SDK CODE Samples","year":"2011"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/InPar.2012.6339595"},{"key":"ref28","article-title":"NVIDIA's Next Generation CUDA Compute Architecture: Fermi","year":"2009"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/2540708.2540718"},{"key":"ref27","article-title":"PTX: Parallel Thread Execution ISA Version 2.3","year":"2011"},{"key":"ref3","first-page":"157","article-title":"Neither More Nor Less: Optimizing Thread-Level Parallelism for GPGPUs","author":"kayiran","year":"2013","journal-title":"International Conference on Parallel Architectures and Compilation Techniques (PACT)"},{"key":"ref6","article-title":"Better Performance at Lower Occupancy","author":"volkov","year":"2010"},{"key":"ref29","article-title":"GPGPU-Sim Manual","year":"0"},{"key":"ref5","article-title":"Whitepaper: NVIDIA GeForce GTX 680","year":"0"},{"key":"ref8","article-title":"Tuning CUDA Applications for Kepler","year":"2013"},{"key":"ref7","article-title":"NVIDIA's Next Generation CUDA Compute Architecture: Kepler GK110","year":"0","journal-title":"NVIDIA white paper"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2012.16"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2009.4919648"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/L-CA.2009.4"},{"key":"ref20","article-title":"Parboil Benchmark Suite","year":"0"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC.2009.5306797"},{"key":"ref21","doi-asserted-by":"crossref","first-page":"260","DOI":"10.1145\/1454115.1454152","article-title":"A MapReduce Framework on Graphics Processors","author":"he","year":"2008","journal-title":"International Conference on Parallel Architectures and Compilation Techniques (PACT)"},{"key":"ref24","article-title":"Co-Design for Molecular Dynamics: An Exascale Proxy Application","author":"mohd-yusof","year":"2013"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC.2012.6402918"},{"key":"ref26","article-title":"NVIDIA CUDA Programming Guide","year":"2011"},{"key":"ref25","article-title":"GPGPU-Sim","year":"0"}],"event":{"name":"2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA)","location":"Burlingame, CA, USA","start":{"date-parts":[[2015,2,7]]},"end":{"date-parts":[[2015,2,11]]}},"container-title":["2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7048058\/7056013\/07056024.pdf?arnumber=7056024","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,5,1]],"date-time":"2022-05-01T17:44:02Z","timestamp":1651427042000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7056024\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,2]]},"references-count":32,"URL":"https:\/\/doi.org\/10.1109\/hpca.2015.7056024","relation":{},"subject":[],"published":{"date-parts":[[2015,2]]}}}