{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,9,18]],"date-time":"2026-09-18T09:42:05Z","timestamp":1789724525053,"version":"4.0.1"},"reference-count":37,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2015,2]]},"DOI":"10.1109\/hpca.2015.7056027","type":"proceedings-article","created":{"date-parts":[[2015,3,10]],"date-time":"2015-03-10T18:13:51Z","timestamp":1426011231000},"page":"126-136","source":"Crossref","is-referenced-by-count":130,"title":["Heterogeneous memory architectures: A HW\/SW approach for mixing die-stacked and off-package memories"],"prefix":"10.1109","author":[{"given":"Mitesh R.","family":"Meswani","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Sergey","family":"Blagodurov","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"David","family":"Roberts","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"John","family":"Slice","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Mike","family":"Ignatowski","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Gabriel H.","family":"Loh","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2011.65"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2012.69"},{"key":"ref31","first-page":"1","article-title":"Dimmap—a scalable memory-map runtime for out-of-core data-intensive applications","author":"van essen","year":"2013","journal-title":"Cluster Computing"},{"key":"ref30","first-page":"205","article-title":"Implementing a leading loads performance predictor on commodity processors","author":"su","year":"2014","journal-title":"USENIX ATC'14 Proceedings of the 2014 USENIX Conference on USENIX Annual Technical Conference"},{"key":"ref37","first-page":"91","article-title":"The multi-queue replacement algorithm for second level buffer caches","author":"zhou","year":"2001","journal-title":"Proc 2001 USENIX Ann Technical Conf"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2007.4601880"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2009.30"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1145\/216585.216588"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/CASES.2013.6662515"},{"key":"ref11","year":"0","journal-title":"POWER8 Processor User's Manual for the Single-Chip Module"},{"key":"ref12","year":"0","journal-title":"KnightsLanding"},{"key":"ref13","year":"0","journal-title":"WIDE I\/O Single Data Rate (WIDE I\/O SDR)"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/2485922.2485957"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2010.5416642"},{"key":"ref16","year":"0","journal-title":"JEDEC 3D-ICs"},{"key":"ref17","article-title":"Software-Controlled Transparent Management of Heterogeneous Memory Resources in Virtualized Systems","author":"lee","year":"2014","journal-title":"Proc of the the Workshop on Memory Systems Performance and Correctness"},{"key":"ref18","doi-asserted-by":"crossref","DOI":"10.1145\/2155620.2155673","article-title":"Supporting Very Large Caches with Conventional Block Sizes","author":"loh","year":"2011","journal-title":"Proc 44th IEEE Int'l Symp Microarchitecture"},{"key":"ref19","article-title":"Challenges in Heterogeneous Die-Stacked and Off-Chip Memory Systems","author":"loh","year":"2012","journal-title":"Proc Workshop SoCs Heterogen Archit Workloads (SHAW)"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2012.31"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/74851.74854"},{"key":"ref27","first-page":"13","article-title":"Flashvm: Revisiting the virtual memory hierarchy","author":"saxena","year":"0"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/2597917.2597924"},{"key":"ref6","article-title":"CAMEO:A Two-Level Memory Organization with Capacity of Main Memory and Flexibility of Hardware-Managed Cache","author":"chiachen chou","year":"2014","journal-title":"Proc of the 47th Intl Symp on Microarchitecture"},{"key":"ref29","article-title":"Open Source Real Time Operating System Overview","author":"straumann","year":"2001","journal-title":"Proc of the Int'l Conference on Accelerator and Large Experimental Physics Control Systems"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC.2009.5306797"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.7873\/DATE.2013.032"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/369691.369763"},{"key":"ref2","article-title":"Die Stacking is Happening","author":"black","year":"2013","journal-title":"Proc of the Intl Symp on Microarchitecture"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/SC.Companion.2012.99"},{"key":"ref1","article-title":"Benchmarking modern multiprocessors","author":"bienia","year":"2011"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/L-CA.2012.2"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1145\/2485922.2485927"},{"key":"ref21","year":"0","journal-title":"Micron DDR3 Power Calculator"},{"key":"ref24","article-title":"Hybrid Memory Cube: Breakthrough DRAM Performance with a Fundamentally Re-Architected DRAM Subsystem","author":"pawlowski","year":"2011","journal-title":"Proc 23rd Hot Chips Conf"},{"key":"ref23","year":"0","journal-title":"NVIDIA Pascal"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/IGCC.2011.6008553"},{"key":"ref25","article-title":"Fundamental Latency Trade-offs in Architecturing DRAM Caches: Outperforming Impractical SRAM-Tags with a Simple and Practical Design","author":"qureshi","year":"2012","journal-title":"Proc of 45th Int'l Symp on Microarchitecture"}],"event":{"name":"2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA)","location":"Burlingame, CA, USA","start":{"date-parts":[[2015,2,7]]},"end":{"date-parts":[[2015,2,11]]}},"container-title":["2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7048058\/7056013\/07056027.pdf?arnumber=7056027","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,5,1]],"date-time":"2022-05-01T17:44:29Z","timestamp":1651427069000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7056027\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,2]]},"references-count":37,"URL":"https:\/\/doi.org\/10.1109\/hpca.2015.7056027","relation":{},"subject":[],"published":{"date-parts":[[2015,2]]}}}