{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,21]],"date-time":"2026-02-21T18:18:41Z","timestamp":1771697921942,"version":"3.50.1"},"reference-count":43,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2015,2]]},"DOI":"10.1109\/hpca.2015.7056039","type":"proceedings-article","created":{"date-parts":[[2015,3,10]],"date-time":"2015-03-10T18:13:51Z","timestamp":1426011231000},"page":"271-282","source":"Crossref","is-referenced-by-count":82,"title":["Adrenaline: Pinpointing and reining in tail queries with quick voltage boosting"],"prefix":"10.1109","author":[{"given":"Chang-Hong","family":"Hsu","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yunqi","family":"Zhang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Michael A.","family":"Laurenzano","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"David","family":"Meisner","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Thomas","family":"Wenisch","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jason","family":"Mars","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Lingjia","family":"Tang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ronald G.","family":"Dreslinski","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1145\/2485922.2485975"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1145\/2259016.2259018"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2014.21"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/L-CA.2009.46"},{"key":"ref31","doi-asserted-by":"crossref","first-page":"48","DOI":"10.1145\/1353534.1346289","article-title":"No “Power” Struggles: Coordinated Multi-level Power Management for the Data Center","volume":"36","author":"raghavendra","year":"2008","journal-title":"SIGARCH Comput Archit News"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1145\/2333660.2333727"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1145\/2155620.2155650"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1145\/2451116.2451126"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1145\/2485922.2485974"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2014.53"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2014.52"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1145\/2451116.2451125"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/2150976.2150982"},{"key":"ref12","article-title":"Intel Turbo Boost Technology in Intel Core Microarchitecture (Nehalem) Based Processors","author":"corporation","year":"2008","journal-title":"White Paper"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2009.5424375"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/2189750.2151020"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2012.6189204"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/2254756.2254766"},{"key":"ref17","first-page":"319","article-title":"Power management of online data-intensive services","author":"meisner","year":"2011","journal-title":"2011 38th Annual International Symposium on Computer Architecture (ISCA) ISCA"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/2528521.1508269"},{"key":"ref19","first-page":"385","article-title":"Scaling Memcache at Facebook","author":"nishtala","year":"2013","journal-title":"Proceedings of the 10th USENIX Conference on Networked Systems Design and Implementation nsdi'13"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1145\/1998582.1998590"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2014.6853237"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2012.22"},{"key":"ref3","first-page":"10","article-title":"Pitfalls of Accurately Benchmarking Thermally Adaptive Chips","volume":"5","author":"emurian","year":"0","journal-title":"Power (W)"},{"key":"ref6","first-page":"123","article-title":"System level analysis of fast, per-core DVFS using on-chip switching regulators","author":"kim","year":"2008","journal-title":"High Performance Computer Architecture 2008 HPCA 2008 IEEE 14th International Symposium on"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1145\/1950365.1950392"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/2485922.2485926"},{"key":"ref8","first-page":"290c","article-title":"Shortstop: An on-chip fast supply boosting technique","author":"pinckney","year":"2013","journal-title":"2013 Symposium on VLSI Circuits VLSIC"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2011.5746313"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2003.1196112"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2012.6168942"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/2408776.2408794"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2004.839485(410) 24"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.8"},{"key":"ref21","first-page":"271","article-title":"A dynamic compilation framework for controlling microprocessor energy and performance","author":"wu","year":"2005","journal-title":"Proceedings of the 38th annual IEEE\/ACM International Symposium on Microarchitecture"},{"key":"ref42","first-page":"17","article-title":"Decoupling Cores, Kernels, and Operating Systems","author":"zellweger","year":"2014","journal-title":"11th USENIX Symposium on Operating Systems Design and Implementation (OSDI 14)"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1145\/1629911.1629926"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1145\/2342356.2342390"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.2200\/S00119ED1V01Y200805CAC004"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2014.6835969"},{"key":"ref43","first-page":"49","article-title":"IX: A Protected Dataplane Operating System for High Throughput and Low Latency","author":"belay","year":"2014","journal-title":"11th USENIX Symposium on Operating Systems Design and Implementation (OSDI 14)"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2011.5763052"}],"event":{"name":"2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA)","location":"Burlingame, CA, USA","start":{"date-parts":[[2015,2,7]]},"end":{"date-parts":[[2015,2,11]]}},"container-title":["2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7048058\/7056013\/07056039.pdf?arnumber=7056039","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,23]],"date-time":"2017-06-23T03:04:00Z","timestamp":1498187040000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7056039\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,2]]},"references-count":43,"URL":"https:\/\/doi.org\/10.1109\/hpca.2015.7056039","relation":{},"subject":[],"published":{"date-parts":[[2015,2]]}}}