{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,8]],"date-time":"2026-01-08T04:35:10Z","timestamp":1767846910598,"version":"3.49.0"},"reference-count":40,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2015,2]]},"DOI":"10.1109\/hpca.2015.7056045","type":"proceedings-article","created":{"date-parts":[[2015,3,10]],"date-time":"2015-03-10T22:13:51Z","timestamp":1426025631000},"page":"343-353","source":"Crossref","is-referenced-by-count":27,"title":["High performing cache hierarchies for server workloads: Relaxing inclusion to capture the latency benefits of exclusive caches"],"prefix":"10.1109","author":[{"given":"Aamer","family":"Jaleel","sequence":"first","affiliation":[]},{"given":"Joseph","family":"Nuzman","sequence":"additional","affiliation":[]},{"given":"Adrian","family":"Moga","sequence":"additional","affiliation":[]},{"given":"Simon C.","family":"Steely","sequence":"additional","affiliation":[]},{"given":"Joel","family":"Emer","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref39","article-title":"Cache Replacement Policy Revisited","author":"zahran","year":"2007","journal-title":"WDDD"},{"key":"ref38","article-title":"Non-inclusion property in multi-level caches revisited","author":"zahran","year":"2007","journal-title":"IJCAI '07"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1145\/2366231.2337196"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/12.919279"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2004.28"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2009.4798236"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1145\/2155620.2155672"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1145\/2155620.2155671"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2009.4798239"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC.2008.4636095"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1002\/9781119973584.ch13"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2004.1291359"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2010.31"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/2150976.2150982"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/2155620.2155638"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2008.4771774"},{"key":"ref15","article-title":"Techniques for Reducing the Impact of Inclusion in Shared Network Cache Multiprocessors","author":"fletcher","year":"1995","journal-title":"Rice ELEC TR 9413"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/2000064.2000075"},{"key":"ref17","article-title":"Database servers on chip multiprocessors: limitations & opportunities","author":"hardavellas","year":"0","journal-title":"Innovative Data Systems Research"},{"key":"ref18","article-title":"The AMD Athlon XP Processor with 512KB L2 Cache","author":"huynh","year":"2003","journal-title":"White Paper"},{"key":"ref19","article-title":"CMP$im: A Pin-Based On-The-Fly Multi-Core Cache Simulator","author":"jaleel","year":"2008","journal-title":"MOBS"},{"key":"ref28","article-title":"Scale-Out Processors","author":"l-kamran","year":"0","journal-title":"ISCA '12"},{"key":"ref4","year":"0"},{"key":"ref27","article-title":"Cache Replacement with Dynamic Exclusion","author":"mcfarling","year":"0","journal-title":"ISCA'92"},{"key":"ref3","year":"0"},{"key":"ref6","year":"0"},{"key":"ref29","article-title":"Adaptive Insertion Policies for High Performance Caching","author":"qureshi","year":"2006","journal-title":"ISCA"},{"key":"ref5","year":"0","journal-title":"Commercial workload targeted prefetcher was not in the top three performing prefetchers across several server multimedia games scientific and engineering workloads"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1998.694758"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1988.5212"},{"key":"ref2","year":"0","journal-title":"Intel Core I7 Processor"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.10"},{"key":"ref1","year":"0"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/1815961.1815971"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2010.52"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1145\/1454115.1454145"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1994.288163"},{"key":"ref23","author":"jaleel","year":"2007","journal-title":"Memory Characterization of Workloads Using Instrumentation-driven Simulation-a Pin-based Memory Characterization of the SPEC CPU2000 and SPEC CPU2006 Benchmark Suites"},{"key":"ref26","article-title":"Modified L1\/L2 cache inclusion for aggressive prefetch","author":"mayfield","year":"0"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1145\/325164.325162"}],"event":{"name":"2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA)","location":"Burlingame, CA, USA","start":{"date-parts":[[2015,2,7]]},"end":{"date-parts":[[2015,2,11]]}},"container-title":["2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7048058\/7056013\/07056045.pdf?arnumber=7056045","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,24]],"date-time":"2017-03-24T18:40:21Z","timestamp":1490380821000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7056045\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,2]]},"references-count":40,"URL":"https:\/\/doi.org\/10.1109\/hpca.2015.7056045","relation":{},"subject":[],"published":{"date-parts":[[2015,2]]}}}