{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,8]],"date-time":"2026-01-08T03:14:09Z","timestamp":1767842049825,"version":"3.49.0"},"reference-count":89,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2015,2]]},"DOI":"10.1109\/hpca.2015.7056067","type":"proceedings-article","created":{"date-parts":[[2015,3,10]],"date-time":"2015-03-10T18:13:51Z","timestamp":1426011231000},"page":"615-626","source":"Crossref","is-referenced-by-count":47,"title":["BRAINIAC: Bringing reliable accuracy into neurally-implemented approximate computing"],"prefix":"10.1109","author":[{"given":"Beayna","family":"Grigorian","sequence":"first","affiliation":[]},{"given":"Nazanin","family":"Farahpour","sequence":"additional","affiliation":[]},{"given":"Glenn","family":"Reinman","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref73","doi-asserted-by":"publisher","DOI":"10.1145\/1399504.1360617"},{"key":"ref72","doi-asserted-by":"publisher","DOI":"10.1109\/IJCNN.2008.4633828"},{"key":"ref71","doi-asserted-by":"publisher","DOI":"10.1145\/1993498.1993518"},{"key":"ref70","doi-asserted-by":"publisher","DOI":"10.1145\/2540708.2540711"},{"key":"ref76","doi-asserted-by":"publisher","DOI":"10.1109\/HIPC.2009.5433219"},{"key":"ref77","year":"0","journal-title":"Synopsys Design Compiler"},{"key":"ref74","doi-asserted-by":"publisher","DOI":"10.1145\/2025113.2025133"},{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/92.974895"},{"key":"ref75","doi-asserted-by":"publisher","DOI":"10.1109\/MPUL.2011.2175639"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/FPGA.1997.624600"},{"key":"ref78","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2012.6237031"},{"key":"ref79","first-page":"113","article-title":"Energy-Efficient Motion Estimation Using ErrorTolerance","author":"varatkar","year":"0","journal-title":"ISLPED '06"},{"key":"ref33","first-page":"1","article-title":"Chip Multiprocessing and the Cell Broadband Engine","author":"gschwind","year":"0","journal-title":"CF '06"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/AHS.2014.6880184"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2014.6974700"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2011.5749755"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1145\/1950365.1950385"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1145\/2000064.2000066"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2012.6263960"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2012.2217962"},{"key":"ref60","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2010.5457181"},{"key":"ref62","article-title":"Implementation of a Fast Artificial Neural Network Library (FANN)","author":"nissen","year":"2003","journal-title":"Report"},{"key":"ref61","doi-asserted-by":"crossref","first-page":"177","DOI":"10.1023\/A:1007986707921","article-title":"Approximate Signal Processing","volume":"15","author":"nawab","year":"0","journal-title":"J VLSI Sig Proc '97"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1007\/BF00344251"},{"key":"ref63","doi-asserted-by":"publisher","DOI":"10.1016\/j.patcog.2004.01.013"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/2.32"},{"key":"ref64","doi-asserted-by":"publisher","DOI":"10.1137\/1.9780898719468"},{"key":"ref65","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.1998.703970"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/3477.552199"},{"key":"ref66","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669160"},{"key":"ref67","author":"przytula","year":"1993","journal-title":"Parallel Digital Implementations of Neural Networks"},{"key":"ref68","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2010.202"},{"key":"ref2","year":"0","journal-title":"AMD FireStream GPU Compute Accelerators"},{"key":"ref69","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2010.79"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2014.6853213"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/1815961.1816026"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2003.1253179"},{"key":"ref21","article-title":"A Platform 2015 Workload Model: Recognition, Mining and Synthesis Moves Computers to the Era of Tera","author":"dubey","year":"2007","journal-title":"Intel Corporation White Paper"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2012.48"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1145\/2150976.2151008"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1147\/JRD.2009.2036980"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1145\/1736020.1736063"},{"key":"ref50","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669172"},{"key":"ref51","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2007.346196"},{"key":"ref59","year":"0","journal-title":"Nallatech Intel Xeon FSB-FPGA Accelerator Module"},{"key":"ref58","doi-asserted-by":"publisher","DOI":"10.1016\/j.neucom.2010.03.021"},{"key":"ref57","doi-asserted-by":"crossref","first-page":"92","DOI":"10.1145\/1105734.1105747","article-title":"Multifacet's General Execution-Driven Multiprocessor Simulator Toolset","volume":"33","author":"martin","year":"0","journal-title":"SIGArch Computer Architecture News"},{"key":"ref56","doi-asserted-by":"publisher","DOI":"10.1109\/2.982916"},{"key":"ref55","doi-asserted-by":"publisher","DOI":"10.1145\/2086696.2086727"},{"key":"ref54","first-page":"67","article-title":"Speeding Up Processing with Approximation Circuits","volume":"37","author":"lu","year":"0","journal-title":"Computer '04"},{"key":"ref53","first-page":"132","article-title":"Introduction to Intel Advanced Vector Extensions","author":"lomont","year":"0","journal-title":"ASCI '11"},{"key":"ref52","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2008.31"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC.2012.6402898"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2011.2179038"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1145\/1950365.1950390"},{"key":"ref12","first-page":"903","article-title":"Approximate Logic Circuits for Low Over-head, Non-Intrusive Concurrent Error Detection","author":"choudhury","year":"0","journal-title":"DATE '08"},{"key":"ref13","first-page":"389","article-title":"VEAL: Virtualized Execution Accelerator for Loops","author":"clark","year":"0","journal-title":"ISCA '08"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228512"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/2333660.2333747"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ASAP.2011.6043233"},{"key":"ref82","doi-asserted-by":"publisher","DOI":"10.1145\/2540708.2540710"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1145\/1575774.1575776"},{"key":"ref81","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228504"},{"key":"ref18","article-title":"The Hybrid-Core Series","year":"0","journal-title":"Convey computer"},{"key":"ref84","doi-asserted-by":"publisher","DOI":"10.1109\/70.86079"},{"key":"ref83","doi-asserted-by":"publisher","DOI":"10.1145\/2155620.2155640"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2002.1013301"},{"key":"ref80","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC.2009.5306794"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/2485922.2485923"},{"key":"ref89","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-45234-8_120"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/1806596.1806620"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2010.11"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/1454115.1454128"},{"key":"ref8","first-page":"33","article-title":"Verifying Quantitative Reliability for Programs That Execute on Unreliable Hardware","author":"carbin","year":"0","journal-title":"OOPSLA'13"},{"key":"ref85","doi-asserted-by":"publisher","DOI":"10.1145\/1250734.1250753"},{"key":"ref7","article-title":"Box2D: A 2D Physics Engine for Games","year":"0","journal-title":"Box2d"},{"key":"ref86","year":"0","journal-title":"Xilinx"},{"key":"ref49","doi-asserted-by":"publisher","DOI":"10.1145\/2000064.2000080"},{"key":"ref87","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.9"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2006.243978"},{"key":"ref88","doi-asserted-by":"publisher","DOI":"10.1109\/5326.897072"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2009.5090700"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1145\/1231996.1232000"},{"key":"ref48","doi-asserted-by":"publisher","DOI":"10.1109\/72.554195"},{"key":"ref47","doi-asserted-by":"publisher","DOI":"10.1109\/IJCNN.1990.137572"},{"key":"ref42","year":"0","journal-title":"CACTI 5 3"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/IJCNN.1989.118698"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1109\/DICTA.2008.82"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228450"}],"event":{"name":"2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA)","location":"Burlingame, CA, USA","start":{"date-parts":[[2015,2,7]]},"end":{"date-parts":[[2015,2,11]]}},"container-title":["2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7048058\/7056013\/07056067.pdf?arnumber=7056067","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,23]],"date-time":"2017-06-23T03:03:59Z","timestamp":1498187039000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7056067\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,2]]},"references-count":89,"URL":"https:\/\/doi.org\/10.1109\/hpca.2015.7056067","relation":{},"subject":[],"published":{"date-parts":[[2015,2]]}}}