{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,21]],"date-time":"2026-02-21T19:03:02Z","timestamp":1771700582003,"version":"3.50.1"},"reference-count":68,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2016,3]]},"DOI":"10.1109\/hpca.2016.7446056","type":"proceedings-article","created":{"date-parts":[[2016,4,4]],"date-time":"2016-04-04T22:03:56Z","timestamp":1459807436000},"page":"90-101","source":"Crossref","is-referenced-by-count":33,"title":["CompEx: Compression-expansion coding for energy, latency, and lifetime improvements in MLC\/TLC NVM"],"prefix":"10.1109","author":[{"given":"Poovaiah M.","family":"Palangappa","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kartik","family":"Mohanram","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1145\/2370816.2370870"},{"key":"ref38","article-title":"Frequent pattern compression: A significance-based compression scheme for L2 caches","author":"alameldeen","year":"2004","journal-title":"University of Wisconsin-Madison Technical Report"},{"key":"ref33","article-title":"Performance analysis of on-chip cache and main memory compression systems for high-end parallel computers","author":"yim","year":"2004","journal-title":"Proc Intl Conference on Parallel and Distributed Processing Techniques and Applications"},{"key":"ref32","article-title":"A limit study on the potential of compression for improving memory system performance, power consumption, and cost","author":"mahapatra","year":"2005","journal-title":"Journal of Instruction-Level Parallelism"},{"key":"ref31","article-title":"Energy efficient frequent value data cache design","author":"yang","year":"2002","journal-title":"Proc Intl Symposium on Microarchitecture"},{"key":"ref30","article-title":"Frequent value compression in data caches","author":"yang","year":"2000","journal-title":"Proc Intl Symposium on Microarchitecture"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2011.6081394"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2012.62"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2012.10"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2005.6"},{"key":"ref60","article-title":"Disintegrated control for energy-efficient and heterogeneous memory systems","author":"ham","year":"2013","journal-title":"Proc Intl Symposium on High Performance Computer Architecture"},{"key":"ref62","author":"hennessy","year":"2011","journal-title":"Computer Architecture A Quantitative Approach"},{"key":"ref61","article-title":"The gem5 simulator","volume":"39","author":"bikerst","year":"2011","journal-title":"IEEE Computer Architecture Letters"},{"key":"ref63","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2011.6131539"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1145\/368122.368872"},{"key":"ref64","doi-asserted-by":"publisher","DOI":"10.1145\/1816038.1815981"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1145\/2540708.2540715"},{"key":"ref65","doi-asserted-by":"publisher","DOI":"10.1145\/2593069.2593217"},{"key":"ref66","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2011.6081426"},{"key":"ref29","article-title":"C-Pack: A highperformance microprocessor cache compression algorithm","author":"chen","year":"2010","journal-title":"IEEE Transactions on Very Large Scale Integration (VLSl) Systems"},{"key":"ref67","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2011.5722206"},{"key":"ref68","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2015.7056056"},{"key":"ref2","article-title":"Highly scalable nonvolatile resistive memory using simple binary oxide driven by asymmetric unipolar voltage pulses","author":"baek","year":"2004","journal-title":"Proc Intl Electron Devices Meeting"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555758"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2011.2165974"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/ICPADS.2012.90"},{"key":"ref21","doi-asserted-by":"crossref","DOI":"10.1145\/1669112.1669117","article-title":"Enhancing lifetime and security of phase change memories via start-gap wear leveling","author":"qureshi","year":"2009","journal-title":"Proc Intl Symposium on Microarchitecture"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2012.6169027"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1145\/1815961.1816014"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/NANOARCH.2014.6880482"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/MASCOTS.2012.39"},{"key":"ref50","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228406"},{"key":"ref51","author":"costello","year":"2004","journal-title":"Error Control Coding"},{"key":"ref59","article-title":"QEMU, a fast and portable dynamic translator","author":"bellard","year":"2005","journal-title":"USENIX Annual Technical Conference"},{"key":"ref58","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2007.363733"},{"key":"ref57","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669157"},{"key":"ref56","article-title":"Improving privacy and lifetime of PCM-based main memory","author":"kong","year":"2010","journal-title":"The International Conference on Dependable Systems and Networks"},{"key":"ref55","doi-asserted-by":"publisher","DOI":"10.1145\/2786763.2694387"},{"key":"ref54","doi-asserted-by":"publisher","DOI":"10.1145\/2000064.2000086"},{"key":"ref53","doi-asserted-by":"publisher","DOI":"10.1145\/1815961.1815980"},{"key":"ref52","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2012.6168941"},{"key":"ref10","article-title":"Memory bandwidth and machine balance in current high performance computers","author":"mccalpin","year":"1995","journal-title":"IEEE Computer Society Technical Committee on Computer Architecture Newsletter"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/2024724.2024954"},{"key":"ref40","article-title":"SPEC CPU2006","year":"2006"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/L-CA.2011.4"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669157"},{"key":"ref14","article-title":"A low power phase change random access memory using a data-comparison write scheme","author":"yang","year":"2010","journal-title":"Proc Intl Symposium on Circuits and Systems"},{"key":"ref15","article-title":"WOM-Code solutions for low latency and high endurance in phase change memory","author":"palangappa","year":"2015","journal-title":"IEEE Transactions on Computers"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/2742060.2742110"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2010.5416645"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/2366231.2337203"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228520"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2006439"},{"key":"ref3","article-title":"International technology roadmap for semiconductors","year":"2011"},{"key":"ref6","article-title":"Write strategies for 2 and 4-bit multi-level phase-change memory","author":"philipp","year":"2007","journal-title":"IEEE Intl Electron Devices Meeting"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/2503210.2503221"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/2333660.2333672"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/2463209.2488867"},{"key":"ref49","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2012.6176872"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2013.6657035"},{"key":"ref46","article-title":"Accelerating write by exploiting PCM asymmetries","author":"yue","year":"2013","journal-title":"Proceedings of the International Symposium on High-Performance Computer Architecture"},{"key":"ref45","doi-asserted-by":"crossref","DOI":"10.1109\/JPROC.2012.2190369","article-title":"Metal oxide RRAM","volume":"100","author":"wong","year":"2012","journal-title":"Proc IEEE"},{"key":"ref48","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.888349"},{"key":"ref47","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2012.6169027"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1145\/1065010.1065034"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2012.82"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2011.6131478"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.908001"}],"event":{"name":"2016 IEEE International Symposium on High Performance Computer Architecture (HPCA)","location":"Barcelona, Spain","start":{"date-parts":[[2016,3,12]]},"end":{"date-parts":[[2016,3,16]]}},"container-title":["2016 IEEE International Symposium on High Performance Computer Architecture (HPCA)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7440961\/7446041\/7446056.pdf?arnumber=7446056","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,6,17]],"date-time":"2022-06-17T01:48:47Z","timestamp":1655430527000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7446056\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,3]]},"references-count":68,"URL":"https:\/\/doi.org\/10.1109\/hpca.2016.7446056","relation":{},"subject":[],"published":{"date-parts":[[2016,3]]}}}