{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,13]],"date-time":"2026-04-13T23:15:45Z","timestamp":1776122145906,"version":"3.50.1"},"reference-count":39,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2016,3]]},"DOI":"10.1109\/hpca.2016.7446087","type":"proceedings-article","created":{"date-parts":[[2016,4,4]],"date-time":"2016-04-04T18:03:56Z","timestamp":1459793036000},"page":"469-480","source":"Crossref","is-referenced-by-count":168,"title":["Best-offset hardware prefetching"],"prefix":"10.1109","author":[{"given":"Pierre","family":"Michaud","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1145\/2155620.2155672"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1145\/859618.859663"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1145\/356887.356892"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1145\/320263.320276"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1145\/142880.142891"},{"key":"ref30","article-title":"A case for (partially) tagged geometric history length branch prediction","author":"seznec","year":"2006","journal-title":"Journal of Instruction Level Parallelism"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2007.346185"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2006.38"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555766"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/12.2208"},{"key":"ref10","year":"2014","journal-title":"Intel Intel 64 and IA-32 architectures optimization reference manual"},{"key":"ref11","article-title":"Access map pattern matching for high performance data cache prefetch","volume":"13","author":"ishii","year":"2011","journal-title":"Journal of Instruction-Level Parallelism"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/2540708.2540730"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/1815961.1815971"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1997.604695"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/325164.325162"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/545214.545237"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1145\/2597917.2597941"},{"key":"ref18","article-title":"Lockup-free instruction fetch\/prefetch cache organization","author":"kroft","year":"1981","journal-title":"ISCA"},{"key":"ref19","article-title":"Reducing DRAM latencies with an integrated memory hierarchy design","author":"lin","year":"2001","journal-title":"HPCA"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1145\/339647.339668"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ICPP.1993.92"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1145\/1250662.1250709"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1998.694770"},{"key":"ref6","year":"2015","journal-title":"DPC-2 2nd Data Prefetching Championship"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1145\/2677956"},{"key":"ref5","year":"2009","journal-title":"DPC-1 1st JILP Data Prefetching Championship"},{"key":"ref8","article-title":"Toward scalable cache only memory architectures","author":"hagersten","year":"1992"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1992.697004"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.39"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.32"},{"key":"ref1","article-title":"Effective hardware-based data prefetching for high-performance processors","volume":"44","author":"chen","year":"1995","journal-title":"IEEE Transactions on Computers"},{"key":"ref20","article-title":"Pin building customized program analysis tools with dynamic instrumentation","author":"luk","year":"2005","journal-title":"PLDI"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2004.1342548"},{"key":"ref21","article-title":"The 3P and 4P cache replacement policies","author":"michaud","year":"2010"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1994.288164"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2004.10030"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2014.6835971"},{"key":"ref25","article-title":"MicroLib: a case for quantitative comparison of micro-architecture mechanisms","author":"gracia p\u00e9rez","year":"2004","journal-title":"Micro"}],"event":{"name":"2016 IEEE International Symposium on High Performance Computer Architecture (HPCA)","location":"Barcelona, Spain","start":{"date-parts":[[2016,3,12]]},"end":{"date-parts":[[2016,3,16]]}},"container-title":["2016 IEEE International Symposium on High Performance Computer Architecture (HPCA)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7440961\/7446041\/7446087.pdf?arnumber=7446087","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2016,9,29]],"date-time":"2016-09-29T21:20:22Z","timestamp":1475184022000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7446087\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,3]]},"references-count":39,"URL":"https:\/\/doi.org\/10.1109\/hpca.2016.7446087","relation":{},"subject":[],"published":{"date-parts":[[2016,3]]}}}