{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,2]],"date-time":"2026-03-02T14:35:48Z","timestamp":1772462148941,"version":"3.50.1"},"reference-count":34,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2016,3]]},"DOI":"10.1109\/hpca.2016.7446098","type":"proceedings-article","created":{"date-parts":[[2016,4,4]],"date-time":"2016-04-04T18:03:56Z","timestamp":1459793036000},"page":"606-617","source":"Crossref","is-referenced-by-count":16,"title":["LiveSim: Going live with microarchitecture simulation"],"prefix":"10.1109","author":[{"given":"Sina","family":"Hassani","sequence":"first","affiliation":[]},{"given":"Gabriel","family":"Southern","sequence":"additional","affiliation":[]},{"given":"Jose","family":"Renau","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1145\/2063384.2063454"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2005.1430562"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2013.6575352"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2014.6844456"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2010.5416636"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.1996.563595"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/12.689650"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/1071690.1064278"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2006.1620785"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2005.1430560"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2014.6844464"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2005.1430578"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2013.6522340"},{"key":"ref18","article-title":"Qemu, a fast and portable dynamic translator","author":"bellard","year":"2005","journal-title":"USENIX Annual Technical Conference"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC.2015.29"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1145\/2333660.2333670"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2003.1206991"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1145\/1555349.1555369"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/605397.605403"},{"key":"ref6","article-title":"ProtoFlex: Co-simulation for component-wise FPGA emulator development","author":"chung","year":"2006","journal-title":"Proc Workshop Architecture Res Using FPGA Platforms"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2013.6557141"},{"key":"ref5","article-title":"On the predictability of program behavior using different input data sets","author":"hsu","year":"2002","journal-title":"Workshop on Interaction Between Compilers and Computer Architecture (INTERACT-12)"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2007.363733"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.36"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2007.39"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2003.1238020"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/L-CA.2002.8"},{"key":"ref20","article-title":"Understanding multicore performance: Efficient memory system modeling and simulation","author":"sandberg","year":"2014"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/CGO.2007.35"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/CGO.2007.37"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2003.1190246"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2001.955000"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/SBAC-PAD.2004.38"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1093\/comjnl\/bxh103"}],"event":{"name":"2016 IEEE International Symposium on High Performance Computer Architecture (HPCA)","location":"Barcelona, Spain","start":{"date-parts":[[2016,3,12]]},"end":{"date-parts":[[2016,3,16]]}},"container-title":["2016 IEEE International Symposium on High Performance Computer Architecture (HPCA)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7440961\/7446041\/7446098.pdf?arnumber=7446098","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2016,9,29]],"date-time":"2016-09-29T21:20:29Z","timestamp":1475184029000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7446098\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,3]]},"references-count":34,"URL":"https:\/\/doi.org\/10.1109\/hpca.2016.7446098","relation":{},"subject":[],"published":{"date-parts":[[2016,3]]}}}