{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,5]],"date-time":"2026-03-05T15:33:49Z","timestamp":1772724829701,"version":"3.50.1"},"reference-count":31,"publisher":"IEEE","license":[{"start":{"date-parts":[[2023,2,1]],"date-time":"2023-02-01T00:00:00Z","timestamp":1675209600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2023,2,1]],"date-time":"2023-02-01T00:00:00Z","timestamp":1675209600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2023,2]]},"DOI":"10.1109\/hpca56546.2023.10070977","type":"proceedings-article","created":{"date-parts":[[2023,3,24]],"date-time":"2023-03-24T13:42:55Z","timestamp":1679665375000},"page":"247-258","source":"Crossref","is-referenced-by-count":12,"title":["HIRAC: A Hierarchical Accelerator with Sorting-based Packing for SpGEMMs in DNN Applications"],"prefix":"10.1109","author":[{"given":"Hesam","family":"Shabani","sequence":"first","affiliation":[{"name":"Lehigh University,USA"}]},{"given":"Abhishek","family":"Singh","sequence":"additional","affiliation":[{"name":"Lehigh University,USA"}]},{"given":"Bishoy","family":"Youhana","sequence":"additional","affiliation":[{"name":"Lehigh University,USA"}]},{"given":"Xiaochen","family":"Guo","sequence":"additional","affiliation":[{"name":"Lehigh University,USA"}]}],"member":"263","reference":[{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/3079856.3080246"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2013.6557149"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/2751205.2751209"},{"key":"ref14","article-title":"Packing Sparse Convolutional Neural Networks for Efficient Systolic Array Implementations: Column Combining Under Joint Optimization","author":"kung","year":"2019","journal-title":"Proceedings of the fourth international conference on Architectural support for programming languages and operating systems - AS"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1016\/j.jpdc.2014.03.002"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA47549.2020.00030"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA52012.2021.00011"},{"key":"ref10","article-title":"NLP Architect by Intel AI Lab","year":"2018"},{"key":"ref2","article-title":"NVIDIA","author":"anzt","year":"2014","journal-title":"Implementing a sparse matrix vector product for the sell-c\/sell-c-? formats on nvidia gpus"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-32001-4_92-1"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1145\/3466752.3480125"},{"key":"ref16","article-title":"Rethinking the Value of Network Pruning","author":"liu","year":"2019","journal-title":"International Conference on Learning Representations"},{"key":"ref19","article-title":"Matrix Multiplication Background User’s Guide :: NVIDIA Deep Learning Performance Documentation","year":"2022"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1016\/j.ipl.2004.01.014"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO50266.2020.00068"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1145\/3532863"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA52012.2021.00088"},{"key":"ref25","article-title":"Synopsys Standard Cell Libraries","year":"2019"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA47549.2020.00015"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1145\/3352460.3358302"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1145\/3489517.3530506"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1145\/3543068"},{"key":"ref27","article-title":"S2Engine: A Novel Systolic Architecture for Sparse Convolutional Neural Networks","volume":"71","author":"yang","year":"2022","journal-title":"IEEE Transactions on Computers"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1145\/3445814.3446702"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2018.00062"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/3392717.3392751"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA51647.2021.00017"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2016.7418007"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/3085572"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/3007787.3001163"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JETCAS.2019.2910232"}],"event":{"name":"2023 IEEE International Symposium on High-Performance Computer Architecture (HPCA)","location":"Montreal, QC, Canada","start":{"date-parts":[[2023,2,25]]},"end":{"date-parts":[[2023,3,1]]}},"container-title":["2023 IEEE International Symposium on High-Performance Computer Architecture (HPCA)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/10070856\/10070923\/10070977.pdf?arnumber=10070977","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,4,17]],"date-time":"2023-04-17T13:35:26Z","timestamp":1681738526000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10070977\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,2]]},"references-count":31,"URL":"https:\/\/doi.org\/10.1109\/hpca56546.2023.10070977","relation":{},"subject":[],"published":{"date-parts":[[2023,2]]}}}