{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,5]],"date-time":"2026-03-05T15:37:15Z","timestamp":1772725035011,"version":"3.50.1"},"reference-count":56,"publisher":"IEEE","license":[{"start":{"date-parts":[[2023,2,1]],"date-time":"2023-02-01T00:00:00Z","timestamp":1675209600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2023,2,1]],"date-time":"2023-02-01T00:00:00Z","timestamp":1675209600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2023,2]]},"DOI":"10.1109\/hpca56546.2023.10071070","type":"proceedings-article","created":{"date-parts":[[2023,3,24]],"date-time":"2023-03-24T17:42:55Z","timestamp":1679679775000},"page":"1275-1288","source":"Crossref","is-referenced-by-count":14,"title":["CHOPPER: A Compiler Infrastructure for Programmable Bit-serial SIMD Processing Using Memory in DRAM"],"prefix":"10.1109","author":[{"given":"Xiangjun","family":"Peng","sequence":"first","affiliation":[{"name":"The Chinese University of Hong Kong"}]},{"given":"Yaohua","family":"Wang","sequence":"additional","affiliation":[{"name":"National University of Defense Technology"}]},{"given":"Ming-Chang","family":"Yang","sequence":"additional","affiliation":[{"name":"The Chinese University of Hong Kong"}]}],"member":"263","reference":[{"key":"ref1","article-title":"6th Generation Intel\u00ae Processor Families for S-Platforms"},{"key":"ref2","article-title":"JEDEC DDR4 SDRAM Standard"},{"key":"ref3","article-title":"NVIDIA TITAN V GPU Specifications"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.5555\/3026877.3026899"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/2872887.2750386"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2019.2945617"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/3466752.3480133"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ICCVW.2019.00244"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1007\/BFb0052352"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/2024716.2024718"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2016.7446095"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/HOTCHIPS.2019.8875680"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2018.00040"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO56248.2022.00067"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-48319-5_19"},{"key":"ref16","article-title":"The Scc Compiler: SWARing at MMX 3DNow!","author":"Fisher","year":"1999","journal-title":"LCPC"},{"key":"ref17","article-title":"General-Purpose SIMD Within a Register: Parallel Processing on Consumer Microprocessors","volume-title":"PhD Thesis","author":"Fisher","year":"2003"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/966049.781505"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1145\/3466752.3480078"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/3352460.3358260"},{"key":"ref21","article-title":"High-Order Entropy-Compressed Text Indexes","author":"Grossi","year":"2003","journal-title":"SODA"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1145\/3445814.3446749"},{"key":"ref23","article-title":"Mapping Irregular Applications to DIVA, a PIM-based Data-Intensive Architecture","author":"Hall","year":"1999","journal-title":"SC"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO50266.2020.00040"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1145\/3130348.3130372"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1145\/3130348.3130372"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2017.243"},{"key":"ref28","volume-title":"Memory Systems: Cache, DRAM, Disk.","author":"Jacob","year":"2010"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1145\/3341301.3359630"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1145\/2366231.2337202"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/LCA.2015.2414456"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/CGO.2004.1281665"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.46506\/jica.2021.2.1.043"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA47549.2020.00052"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1145\/3123939.3123977"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1145\/2897937.2898064"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1145\/3314221.3314636"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1145\/3178433.3178437"},{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1145\/2020408.2020487"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO56248.2022.00060"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1145\/279361.279387"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO56248.2022.00069"},{"key":"ref43","article-title":"PyTorch: An Imperative Style, High-Performance Deep Learning Library","author":"Paszke","year":"2019","journal-title":"NIPS"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1109\/40.592312"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1145\/330249.330250"},{"key":"ref46","article-title":"Automatic Software Optimization of Block Ciphers using Bitslicing Techniques","author":"Pornin","year":"1999","journal-title":"Ecole Normale Superieure"},{"key":"ref47","article-title":"Implantation Et Optimisation DES Primitives Cryptographiques","author":"Pornin","year":"2001"},{"key":"ref48","doi-asserted-by":"publisher","DOI":"10.1145\/342001.339668"},{"key":"ref49","doi-asserted-by":"publisher","DOI":"10.1145\/2540708.2540725"},{"key":"ref50","doi-asserted-by":"publisher","DOI":"10.1145\/3123939.3124544"},{"key":"ref51","doi-asserted-by":"publisher","DOI":"10.1109\/DCC.2015.7"},{"key":"ref52","article-title":"MQSim: A Framework for Enabling Realistic Studies of Modern Multi-Queue SSD Devices","author":"Tavakkol","year":"2018","journal-title":"FAST"},{"key":"ref53","doi-asserted-by":"publisher","DOI":"10.1145\/3466752.3480071"},{"key":"ref54","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO50266.2020.00036"},{"key":"ref55","article-title":"Controller for A Synchronous DRAM that Maximizes Throughput by Allowing Memory Requests and Commands to be Issued Out of Order","volume-title":"US Patent","author":"Zuravleff","year":"1997"},{"key":"ref56","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA47549.2020.00033"}],"event":{"name":"2023 IEEE International Symposium on High-Performance Computer Architecture (HPCA)","location":"Montreal, QC, Canada","start":{"date-parts":[[2023,2,25]]},"end":{"date-parts":[[2023,3,1]]}},"container-title":["2023 IEEE International Symposium on High-Performance Computer Architecture (HPCA)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/10070856\/10070923\/10071070.pdf?arnumber=10071070","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,2,13]],"date-time":"2024-02-13T13:27:19Z","timestamp":1707830839000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10071070\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,2]]},"references-count":56,"URL":"https:\/\/doi.org\/10.1109\/hpca56546.2023.10071070","relation":{},"subject":[],"published":{"date-parts":[[2023,2]]}}}