{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,11]],"date-time":"2026-04-11T13:21:17Z","timestamp":1775913677512,"version":"3.50.1"},"reference-count":64,"publisher":"IEEE","license":[{"start":{"date-parts":[[2023,2,1]],"date-time":"2023-02-01T00:00:00Z","timestamp":1675209600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2023,2,1]],"date-time":"2023-02-01T00:00:00Z","timestamp":1675209600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/100000028","name":"Semiconductor Research Corporation","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100000028","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2023,2]]},"DOI":"10.1109\/hpca56546.2023.10071074","type":"proceedings-article","created":{"date-parts":[[2023,3,24]],"date-time":"2023-03-24T17:42:55Z","timestamp":1679679775000},"page":"691-704","source":"Crossref","is-referenced-by-count":12,"title":["EVE: Ephemeral Vector Engines"],"prefix":"10.1109","author":[{"given":"Khalid","family":"Al-Hawaj","sequence":"first","affiliation":[{"name":"Cornell University,School of Electrical and Computer Engineering,Ithaca,NY"}]},{"given":"Tuan","family":"Ta","sequence":"additional","affiliation":[{"name":"Cornell University,School of Electrical and Computer Engineering,Ithaca,NY"}]},{"given":"Nick","family":"Cebry","sequence":"additional","affiliation":[{"name":"Cornell University,School of Electrical and Computer Engineering,Ithaca,NY"}]},{"given":"Shady","family":"Agwa","sequence":"additional","affiliation":[{"name":"Cornell University,School of Electrical and Computer Engineering,Ithaca,NY"}]},{"given":"Olalekan","family":"Afuye","sequence":"additional","affiliation":[{"name":"Cornell University,School of Electrical and Computer Engineering,Ithaca,NY"}]},{"given":"Eric","family":"Hall","sequence":"additional","affiliation":[{"name":"Cornell University,School of Electrical and Computer Engineering,Ithaca,NY"}]},{"given":"Courtney","family":"Golden","sequence":"additional","affiliation":[{"name":"Cornell University,School of Electrical and Computer Engineering,Ithaca,NY"}]},{"given":"Alyssa B.","family":"Apsel","sequence":"additional","affiliation":[{"name":"Cornell University,School of Electrical and Computer Engineering,Ithaca,NY"}]},{"given":"Christopher","family":"Batten","sequence":"additional","affiliation":[{"name":"Cornell University,School of Electrical and Computer Engineering,Ithaca,NY"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/1362622.1362646"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2017.21"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2018.2848999"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2019.2907488"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/2749469.2750386"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS45731.2020.9181068"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/2024716.2024718"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA51647.2021.00054"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/tvlsi.2019.2950087"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA45697.2020.00044"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC.2009.5306797"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA45697.2020.00016"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/3061639.3062326"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2016.13"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2017.8"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2005.20"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2018.00040"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/54.748803"},{"key":"ref19","doi-asserted-by":"crossref","DOI":"10.1145\/2000064.2000108","article-title":"Dark Silicon and the End of Multicore Scaling","volume-title":"Int\u2019l Symp. on Computer Architecture","author":"Esmaeilzadeh"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2002.1003586"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2015.7056040"},{"key":"ref22","volume-title":"Content Addressable Parallel Processors.","author":"Foster","year":"1976"},{"key":"ref23","doi-asserted-by":"crossref","DOI":"10.1145\/3307650.3322257","article-title":"Duality Cache for Data Parallel Acceleration","volume-title":"Int\u2019l Symp. on Computer Architecture","author":"Fujiki"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1145\/3352460.3358260"},{"key":"ref25","article-title":"Arm\u2019s AMBA 5 CHI Ruby Model in gem5. Online Webpage"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1145\/2508148.2485939"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1145\/2966986.2980098"},{"key":"ref28","doi-asserted-by":"crossref","DOI":"10.1145\/3307650.3322237","article-title":"FloatPIM: In-Memory Acceleration of Deep Neural Network Training with High Precision","volume-title":"Int\u2019l Symp. on Computer Architecture","author":"Imani"},{"key":"ref29","article-title":"Intel SSE4 Programming Reference","volume-title":"Intel Reference Manual","year":"2007"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2015.7231285"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2515510"},{"issue":"1","key":"ref32","first-page":"2","article-title":"A Hardware Overview of SX-6 and SX-7 Supercomputer","volume":"44","author":"Kitagawa","year":"2003","journal-title":"NEC Research & Development Journal"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1145\/3240302.3240312"},{"key":"ref34","first-page":"288","article-title":"DRISA: A DRAM-based Reconfigurable In-Situ Accelerator","volume-title":"2017 IEEE\/ACM 50th International Symposium on Microarchitecture MICRO, Boston, MA, USA","author":"Li"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA45697.2020.00073"},{"key":"ref36","article-title":"The gem5 Simulator: Version 20.0+","author":"Lowe-Power","year":"2020"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1145\/2845084"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1998.694774"},{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/40.592312"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/40.526924"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA47549.2020.00034"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1145\/3422667"},{"key":"ref43","article-title":"RISC-V \u201cV\u201d Vector Extension","year":"2019"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2019.2897556"},{"issue":"1","key":"ref45","doi-asserted-by":"crossref","first-page":"63","DOI":"10.1145\/359327.359336","article-title":"The Cray-1 Computer System","volume":"21","author":"Russel","year":"1978","journal-title":"Communications of the ACM"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1109\/ISPDC51135.2020.00009"},{"key":"ref47","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-66400-7_9"},{"key":"ref48","doi-asserted-by":"publisher","DOI":"10.1109\/2.330039"},{"key":"ref49","doi-asserted-by":"crossref","DOI":"10.1145\/2540708.2540725","article-title":"RowClone: Fast and Energy-Efficient In-DRAM Bulk Data Copy and Initialization","volume-title":"Int\u2019l Symp. on Microarchitecture","author":"Seshadri"},{"key":"ref50","first-page":"273","article-title":"Ambit: In-Memory Accelerator for Bulk Bitwise Operations Using Commodity DRAM Technology","volume-title":"2017 IEEE\/ACM 50th International Symposium on Microarchitecture MICRO, Boston, MA, USA","author":"Seshadri"},{"key":"ref51","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2021.3073254"},{"key":"ref52","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2020.2972528"},{"key":"ref53","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2016.25"},{"key":"ref54","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2017.55"},{"key":"ref55","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2018.00052"},{"key":"ref56","doi-asserted-by":"publisher","DOI":"10.1109\/HOTCHIPS.2016.7936203"},{"key":"ref57","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2017.35"},{"key":"ref58","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2017.35"},{"key":"ref59","article-title":"Simulating Multi-Core RISC-V Systems in gem5","volume-title":"Workshop on Computer Architecture Research with RISC-V","author":"Ta"},{"key":"ref60","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-35074-8_1"},{"key":"ref61","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2019.8662419"},{"key":"ref62","doi-asserted-by":"publisher","DOI":"10.1109\/ICECS.2018.8617925"},{"key":"ref63","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2013.220"},{"key":"ref64","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA45697.2020.00074"}],"event":{"name":"2023 IEEE International Symposium on High-Performance Computer Architecture (HPCA)","location":"Montreal, QC, Canada","start":{"date-parts":[[2023,2,25]]},"end":{"date-parts":[[2023,3,1]]}},"container-title":["2023 IEEE International Symposium on High-Performance Computer Architecture (HPCA)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/10070856\/10070923\/10071074.pdf?arnumber=10071074","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,2,13]],"date-time":"2024-02-13T13:19:10Z","timestamp":1707830350000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10071074\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,2]]},"references-count":64,"URL":"https:\/\/doi.org\/10.1109\/hpca56546.2023.10071074","relation":{},"subject":[],"published":{"date-parts":[[2023,2]]}}}