{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,14]],"date-time":"2026-01-14T15:48:40Z","timestamp":1768405720793,"version":"3.49.0"},"reference-count":57,"publisher":"IEEE","license":[{"start":{"date-parts":[[2023,2,1]],"date-time":"2023-02-01T00:00:00Z","timestamp":1675209600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2023,2,1]],"date-time":"2023-02-01T00:00:00Z","timestamp":1675209600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2023,2]]},"DOI":"10.1109\/hpca56546.2023.10071128","type":"proceedings-article","created":{"date-parts":[[2023,3,24]],"date-time":"2023-03-24T17:42:55Z","timestamp":1679679775000},"page":"471-484","source":"Crossref","is-referenced-by-count":13,"title":["Ah-Q: Quantifying and Handling the Interference within a Datacenter from a System Perspective"],"prefix":"10.1109","author":[{"given":"Yuhang","family":"Liu","sequence":"first","affiliation":[{"name":"Institute of Computing Technology, Chinese Academy of Sciences,State Key Lab of Processors,Beijing,China"}]},{"given":"Xin","family":"Deng","sequence":"additional","affiliation":[{"name":"Institute of Computing Technology, Chinese Academy of Sciences,State Key Lab of Processors,Beijing,China"}]},{"given":"Jiapeng","family":"Zhou","sequence":"additional","affiliation":[{"name":"Institute of Computing Technology, Chinese Academy of Sciences,State Key Lab of Processors,Beijing,China"}]},{"given":"Mingyu","family":"Chen","sequence":"additional","affiliation":[{"name":"Institute of Computing Technology, Chinese Academy of Sciences,State Key Lab of Processors,Beijing,China"}]},{"given":"Yungang","family":"Bao","sequence":"additional","affiliation":[{"name":"Institute of Computing Technology, Chinese Academy of Sciences,State Key Lab of Processors,Beijing,China"}]}],"member":"263","reference":[{"key":"ref1","article-title":"Redis","year":"2022"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-31865-1_2"},{"key":"ref3","first-page":"72","article-title":"The parsec benchmark suite: Characterization and architectural implications","volume-title":"Proceedings of the 17th International conference on Parallel Architectures and Compilation Techniques (PACT)","author":"Bienia"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2008.4771801"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/2493123.2462904"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-30599-8_20"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/SC41405.2020.00036"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/3297858.3304005"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/1807128.1807152"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/2499368.2451125"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/2644865.2541941"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/3093337.3037703"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/MSP.2012.2211477"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2018.00019"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1017\/CBO9781139939690"},{"key":"ref16","first-page":"281","article-title":"Caladan: Mitigating interference at microsecond timescales","volume-title":"Proceedings of the 14th USENIX Symposium on Operating Systems Design and Implementation (OSDI 20)","author":"Fried"},{"issue":"11","key":"ref17","article-title":"Intel\u00ae 64 and ia-32 architectures software developer\u2019s manual","volume":"2","author":"Guide","year":"2011","journal-title":"Volume 3B: System programming Guide, Part"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/3326285.3329074"},{"key":"ref19","article-title":"Improving real-time performance by utilizing cache allocation technology","year":"2015","journal-title":"Intel Corporation"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/SC.2012.78"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1145\/2830772.2830797"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1145\/2644865.2541944"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC.2016.7581261"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.3115\/1557769.1557821"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO50266.2020.00060"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2014.6853237"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1145\/2749469.2749475"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1145\/2168836.2168855"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2019.00024"},{"key":"ref30","first-page":"248","article-title":"Bubble-up: Increasing utilization in modern warehouse scale computers via sensible co-locations","volume-title":"Proceedings of the 44th annual IEEE\/ACM International Symposium on Microarchitecture","author":"Mars"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1145\/1944862.1944887"},{"key":"ref32","first-page":"19","article-title":"Memory bandwidth and machine balance in current high performance computers","volume":"2","author":"McCalpin","year":"1995","journal-title":"IEEE computer society technical committee on computer architecture (TCCA) newsletter"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA47549.2020.00023"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS47924.2020.00079"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1145\/3302424.3303963"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA47549.2020.00025"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2020.2996031"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1145\/2016604.2016647"},{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2017.19"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1002\/j.1538-7305.1948.tb01338.x"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1145\/378993.379244"},{"key":"ref42","article-title":"Unfair data centers for fun and profit","author":"Sriraman","year":"2019","journal-title":"Wild and Crazy Ideas (ASPLOS)"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1145\/2830772.2830803"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1631\/FITEE.1800501"},{"key":"ref45","first-page":"2214","article-title":"Parallel data, tools and interfaces in opus","volume":"2012","author":"Tiedemann","year":"2012","journal-title":"Lrec"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1145\/2517349.2522713"},{"key":"ref47","doi-asserted-by":"publisher","DOI":"10.1109\/MASCOTS.2019.00041"},{"key":"ref48","doi-asserted-by":"publisher","DOI":"10.1109\/MASCOTS.2017.11"},{"key":"ref49","doi-asserted-by":"publisher","DOI":"10.1038\/530144a"},{"key":"ref50","article-title":"Sphinx-4: A flexible open source framework for speech recognition","volume":"12","author":"Walker","year":"2004","journal-title":"Sun Microsystems"},{"key":"ref51","doi-asserted-by":"publisher","DOI":"10.1145\/3139291"},{"key":"ref52","doi-asserted-by":"publisher","DOI":"10.1145\/2523616.2523620"},{"key":"ref53","doi-asserted-by":"publisher","DOI":"10.1145\/2508148.2485974"},{"key":"ref54","article-title":"Spark: Cluster computing with working sets","volume-title":"2nd USENIX Workshop on Hot Topics in Cloud Computing (HotCloud 10)","author":"Zaharia"},{"key":"ref55","doi-asserted-by":"publisher","DOI":"10.1145\/2465351.2465388"},{"key":"ref56","doi-asserted-by":"publisher","DOI":"10.1145\/3445814.3446693"},{"key":"ref57","doi-asserted-by":"publisher","DOI":"10.1145\/3342195.3387534"}],"event":{"name":"2023 IEEE International Symposium on High-Performance Computer Architecture (HPCA)","location":"Montreal, QC, Canada","start":{"date-parts":[[2023,2,25]]},"end":{"date-parts":[[2023,3,1]]}},"container-title":["2023 IEEE International Symposium on High-Performance Computer Architecture (HPCA)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/10070856\/10070923\/10071128.pdf?arnumber=10071128","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,2,13]],"date-time":"2024-02-13T13:19:17Z","timestamp":1707830357000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10071128\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,2]]},"references-count":57,"URL":"https:\/\/doi.org\/10.1109\/hpca56546.2023.10071128","relation":{},"subject":[],"published":{"date-parts":[[2023,2]]}}}