{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,5]],"date-time":"2026-03-05T07:51:38Z","timestamp":1772697098560,"version":"3.50.1"},"reference-count":36,"publisher":"IEEE","license":[{"start":{"date-parts":[[2026,1,31]],"date-time":"2026-01-31T00:00:00Z","timestamp":1769817600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2026,1,31]],"date-time":"2026-01-31T00:00:00Z","timestamp":1769817600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2026,1,31]]},"DOI":"10.1109\/hpca68181.2026.11408615","type":"proceedings-article","created":{"date-parts":[[2026,3,4]],"date-time":"2026-03-04T20:47:22Z","timestamp":1772657242000},"page":"1-14","source":"Crossref","is-referenced-by-count":0,"title":["An Efficient and Scalable Hardware Architecture for Number Theoretic Transform on FPGA with Design Automation"],"prefix":"10.1109","author":[{"given":"Yilan","family":"Zhu","sequence":"first","affiliation":[{"name":"Ant Group,Hangzhou,China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Geng","family":"Yang","sequence":"additional","affiliation":[{"name":"Ant Group,Hangzhou,China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Xingyu","family":"Tian","sequence":"additional","affiliation":[{"name":"Simon Fraser University,Burnaby,BC,Canada"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Dilshan","family":"Kumarathunga","sequence":"additional","affiliation":[{"name":"Simon Fraser University,Burnaby,BC,Canada"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Liang","family":"Kong","sequence":"additional","affiliation":[{"name":"Ant Group,Hangzhou,China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Xianglong","family":"Deng","sequence":"additional","affiliation":[{"name":"Institute of Information Engineering, CAS,Beijing,China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Shengyu","family":"Fan","sequence":"additional","affiliation":[{"name":"Institute of Information Engineering, CAS,Beijing,China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Guang","family":"Fan","sequence":"additional","affiliation":[{"name":"Ant Group,Hangzhou,China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Guiming","family":"Shi","sequence":"additional","affiliation":[{"name":"Tsinghua University,Beijing,China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Lei","family":"Chen","sequence":"additional","affiliation":[{"name":"Ant Group,Hangzhou,China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Bo","family":"Zhang","sequence":"additional","affiliation":[{"name":"Ant Group,Hangzhou,China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yisong","family":"Chang","sequence":"additional","affiliation":[{"name":"Ant Group,Hangzhou,China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Shoumeng","family":"Yan","sequence":"additional","affiliation":[{"name":"Ant Group,Hangzhou,China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Zhenman","family":"Fang","sequence":"additional","affiliation":[{"name":"Simon Fraser University,Burnaby,BC,Canada"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Mingzhe","family":"Zhang","sequence":"additional","affiliation":[{"name":"Ant Group,Hangzhou,China"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref1","year":"2024","journal-title":"Rapidstream tapa compiles task-parallel hls program into highfrequency fpga accelerators"},{"key":"ref2","first-page":"685","article-title":"MAD: memory-aware design techniques for accelerating fully homomorphic encryption","volume-title":"Proceedings of the 56th Annual IEEE\/ACM International Symposium on Microarchitecture, MICRO 2023","author":"Agrawal","year":"2023"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA56546.2023.10070953"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1007\/BF00162341"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-47721-7_24"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-030-77870-5_21"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-32009-5_50"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS58744.2024.10558123"},{"key":"ref9","article-title":"A full RNS variant of approximate homomorphic encryption","author":"Cheon","year":"2018","journal-title":"SAC"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-70694-8_15"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-662-53887-6_1"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1007\/s00145-019-09319-x"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO61859.2024.00033"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA61900.2025.00091"},{"key":"ref15","first-page":"144","article-title":"Somewhat practical fully homomorphic encryption","author":"Fan","year":"2012","journal-title":"IACR Cryptol. ePrint Arch."},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA56546.2023.10071017"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.23919\/DATE58400.2024.10546833"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2024.3377366"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.46586\/tches.v2021.i4.114-148"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/3579371.3589053"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO56248.2022.00086"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1145\/3716368.3735514"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1145\/3676536.3697123"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM62733.2025.00024"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.46586\/tches.v2023.i1.463-500"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/DSD.2019.00045"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.2307\/2007970"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1145\/3466752.3480070"},{"key":"ref29","volume-title":"Microsoft SEAL (release 4.1)","year":"2023"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1016\/0167-8191(87)90018-4"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD57390.2023.10323744"},{"key":"ref32","year":"2025","journal-title":"Vitis unified software platform"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM62733.2025.00038"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1145\/3528416.3530225"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA56546.2023.10070984"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2025.3574481"}],"event":{"name":"2026 IEEE International Symposium on High Performance Computer Architecture (HPCA)","location":"Sydney, Australia","start":{"date-parts":[[2026,1,31]]},"end":{"date-parts":[[2026,2,4]]}},"container-title":["2026 IEEE International Symposium on High Performance Computer Architecture (HPCA)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/11408404\/11408433\/11408615.pdf?arnumber=11408615","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,3,5]],"date-time":"2026-03-05T06:51:39Z","timestamp":1772693499000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11408615\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2026,1,31]]},"references-count":36,"URL":"https:\/\/doi.org\/10.1109\/hpca68181.2026.11408615","relation":{},"subject":[],"published":{"date-parts":[[2026,1,31]]}}}