{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,8,2]],"date-time":"2025-08-02T17:05:44Z","timestamp":1754154344266,"version":"3.41.2"},"reference-count":19,"publisher":"IEEE","license":[{"start":{"date-parts":[[2024,12,13]],"date-time":"2024-12-13T00:00:00Z","timestamp":1734048000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2024,12,13]],"date-time":"2024-12-13T00:00:00Z","timestamp":1734048000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100002367","name":"Chinese Academy of Sciences","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100002367","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2024,12,13]]},"DOI":"10.1109\/hpcc64274.2024.00025","type":"proceedings-article","created":{"date-parts":[[2025,7,23]],"date-time":"2025-07-23T18:33:48Z","timestamp":1753295628000},"page":"111-118","source":"Crossref","is-referenced-by-count":0,"title":["LazyCAT: Efficient Fine-Grained Cache Partitioning with Two Boundaries"],"prefix":"10.1109","author":[{"given":"Chuanqi","family":"Zhang","sequence":"first","affiliation":[{"name":"Chinese Academy of Sciences,State Key Lab of Processors, Institute of Computing Technology,Beijing,China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Xueqi","family":"Li","sequence":"additional","affiliation":[{"name":"Chinese Academy of Sciences,State Key Lab of Processors, Institute of Computing Technology,Beijing,China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ninghui","family":"Sun","sequence":"additional","affiliation":[{"name":"Chinese Academy of Sciences,State Key Lab of Processors, Institute of Computing Technology,Beijing,China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yungang","family":"Bao","sequence":"additional","affiliation":[{"name":"Chinese Academy of Sciences,State Key Lab of Processors, Institute of Computing Technology,Beijing,China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sa","family":"Wang","sequence":"additional","affiliation":[{"name":"Chinese Academy of Sciences,State Key Lab of Processors, Institute of Computing Technology,Beijing,China"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"year":"2015","key":"ref1","article-title":"Improving real-time performance by utilizing cache allocation technology"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/hpca.2008.4658653"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/2628071.2628104"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.38"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/2024723.2000073"},{"key":"ref6","first-page":"213","article-title":"Jigsaw: Scalable software-defined caches","volume-title":"PACT","author":"Beckmann","year":"2013"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2018.00019"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/3190508.3190511"},{"year":"2022","key":"ref9","article-title":"Spec cpu2017"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-77723-6_3"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC.2016.7581261"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2012.6169028"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2010.31"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.49"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/2024716.2024718"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2013.6557168"},{"issue":"4","key":"ref17","first-page":"1","article-title":"Simpoint 3.0: Faster and more flexible program phase analysis","volume":"7","author":"Hamerly","year":"2005","journal-title":"Journal of Instruction Level Parallelism"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/3297858.3304005"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/isscc42614.2022.9731565"}],"event":{"name":"2024 IEEE International Conference on High Performance Computing and Communications (HPCC)","start":{"date-parts":[[2024,12,13]]},"location":"Wuhan, China","end":{"date-parts":[[2024,12,15]]}},"container-title":["2024 IEEE International Conference on High Performance Computing and Communications (HPCC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/11083115\/11083125\/11083190.pdf?arnumber=11083190","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,7,24]],"date-time":"2025-07-24T04:48:17Z","timestamp":1753332497000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11083190\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,12,13]]},"references-count":19,"URL":"https:\/\/doi.org\/10.1109\/hpcc64274.2024.00025","relation":{},"subject":[],"published":{"date-parts":[[2024,12,13]]}}}