{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,4]],"date-time":"2024-09-04T08:12:15Z","timestamp":1725437535274},"reference-count":13,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2010,6]]},"DOI":"10.1109\/hpcs.2010.5547070","type":"proceedings-article","created":{"date-parts":[[2010,8,18]],"date-time":"2010-08-18T14:21:20Z","timestamp":1282141280000},"page":"591-598","source":"Crossref","is-referenced-by-count":0,"title":["Application-driven architecture synthesis of on-chip Multiprocessor systems"],"prefix":"10.1109","author":[{"given":"C","family":"Bobda","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"P","family":"Mahr","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"B","family":"Andres","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"H","family":"Ishebabi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"journal-title":"Message Passing Interface (MPI) Forum","article-title":"MPI Forum","year":"2010","key":"ref10"},{"key":"ref11","first-page":"1","article-title":"TMD-MPI: An MPI Implementation for Multiple Processors Across Multiple FPGAs","author":"salda\u00f1a","year":"2006","journal-title":"FPL"},{"key":"ref12","first-page":"277","article-title":"A Pthreads-Based MPI?1 Implementation for MMU-Less Machines","author":"rico-gallego","year":"2008","journal-title":"International Conference of Reconfigurable Computing and FPGAs ReConFig"},{"journal-title":"Intel MPI Benchmarks 3 2 Software Network","article-title":"Intel MPI Benchmarks","year":"2010","key":"ref13"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/PARELEC.2006.44"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ICPP.2001.952063"},{"article-title":"ISO C\/C++ grammars version 1.2","year":"2010","author":"sigala","key":"ref6"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.1999.807504"},{"key":"ref8","article-title":"Automated Architecture Synthesis for Adaptive Multiprocessors on Chip Systems","author":"bobda","year":"2008","journal-title":"Journal of Microprocessors and Microsystems"},{"key":"ref7","article-title":"Partitioning for Parallelization Using Graph Parsing","author":"mccreary","year":"1991","journal-title":"Technical Report"},{"key":"ref2","first-page":"37","article-title":"SUIF Explorer: an interactive and interprocedural parallelizer","author":"liao","year":"1999","journal-title":"In PPoPP '99 Proceedings of the seventh ACM SIGPLAN symposium on Principles and practice of parallel programming"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/1095408.1095418"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2008.4762398"}],"event":{"name":"Simulation (HPCS 2010)","start":{"date-parts":[[2010,6,28]]},"location":"Caen","end":{"date-parts":[[2010,7,2]]}},"container-title":["2010 International Conference on High Performance Computing &amp; Simulation"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5538704\/5547051\/05547070.pdf?arnumber=5547070","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,19]],"date-time":"2017-03-19T01:10:58Z","timestamp":1489885858000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5547070\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,6]]},"references-count":13,"URL":"https:\/\/doi.org\/10.1109\/hpcs.2010.5547070","relation":{},"subject":[],"published":{"date-parts":[[2010,6]]}}}