{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,29]],"date-time":"2024-10-29T18:06:06Z","timestamp":1730225166351,"version":"3.28.0"},"reference-count":18,"publisher":"IEEE","license":[{"start":{"date-parts":[[2019,7,1]],"date-time":"2019-07-01T00:00:00Z","timestamp":1561939200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2019,7,1]],"date-time":"2019-07-01T00:00:00Z","timestamp":1561939200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2019,7,1]],"date-time":"2019-07-01T00:00:00Z","timestamp":1561939200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2019,7]]},"DOI":"10.1109\/hpcs48598.2019.9188056","type":"proceedings-article","created":{"date-parts":[[2020,9,9]],"date-time":"2020-09-09T16:58:33Z","timestamp":1599670713000},"page":"741-746","source":"Crossref","is-referenced-by-count":0,"title":["Methodology for Decoupled Simulation of SystemVerilog HDL Designs"],"prefix":"10.1109","author":[{"given":"Juan-Jose","family":"Crespo","sequence":"first","affiliation":[]},{"given":"German","family":"Maglione-Mathey","sequence":"additional","affiliation":[]},{"given":"Jose L.","family":"Sanchez","sequence":"additional","affiliation":[]},{"given":"Francisco J.","family":"Alfaro-Cortes","sequence":"additional","affiliation":[]},{"given":"Jesus","family":"Escudero-Sahuquillo","sequence":"additional","affiliation":[]},{"given":"Pedro Javier","family":"Garcia","sequence":"additional","affiliation":[]},{"given":"Francisco J.","family":"Quiles","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"year":"2008","journal-title":"Protocol Buffers Google's Data Interchange Format","key":"ref10"},{"year":"2013","author":"hintjens","journal-title":"Zeromq Messaging for Many Applications","key":"ref11"},{"year":"2013","author":"varda","journal-title":"Cap’n Proto Introduction","key":"ref12"},{"year":"2013","author":"furuhashi","journal-title":"MessagePack","key":"ref13"},{"year":"2007","journal-title":"Apache Thrift","key":"ref14"},{"doi-asserted-by":"publisher","key":"ref15","DOI":"10.1109\/MIC.2006.116"},{"year":"2013","journal-title":"Open source amqp messaging","key":"ref16"},{"year":"2019","author":"crespo","journal-title":"High level modeling integration for hardware description languages","key":"ref17"},{"doi-asserted-by":"publisher","key":"ref18","DOI":"10.1016\/j.micpro.2018.05.011"},{"year":"2009","journal-title":"Open Verification Library","key":"ref4"},{"doi-asserted-by":"publisher","key":"ref3","DOI":"10.3850\/9783981537079_1019"},{"key":"ref6","first-page":"75","article-title":"systemc - a modeling platform supporting multiple design abstractions","author":"panda","year":"2001","journal-title":"International Symposium on System Synthesis (IEEE Cat No 01EX526) ISSS-01"},{"year":"2012","journal-title":"Universal Verification Methodology","key":"ref5"},{"key":"ref8","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1145\/2024716.2024718","article-title":"The gem5 simulator","volume":"39","author":"binkert","year":"2011","journal-title":"ACM SIGARCH Computer Architecture News"},{"key":"ref7","volume":"329","author":"gupta","year":"2012","journal-title":"Co-Synthesis of Hardware and Software for Digital Embedded Systems"},{"key":"ref2","first-page":"1622","article-title":"Securing the Cloud with Reconfigurable Computing: An FPGA Accelerator for Homomorphic Encryption","author":"alessandro cilardo","year":"2016","journal-title":"Design Automation Test in Europe Conference Exhibition (DATE)"},{"doi-asserted-by":"publisher","key":"ref1","DOI":"10.1109\/3PGCIC.2015.187"},{"year":"2017","journal-title":"IEEE Std 1800 2-2017","article-title":"IEEE Standard for SystemVerilog-Unified Hardware Design, Specification, and Verification Language","key":"ref9"}],"event":{"name":"2019 International Conference on High Performance Computing & Simulation (HPCS)","start":{"date-parts":[[2019,7,15]]},"location":"Dublin, Ireland","end":{"date-parts":[[2019,7,19]]}},"container-title":["2019 International Conference on High Performance Computing & Simulation (HPCS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9183768\/9188050\/09188056.pdf?arnumber=9188056","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,7,17]],"date-time":"2022-07-17T17:50:28Z","timestamp":1658080228000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9188056\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,7]]},"references-count":18,"URL":"https:\/\/doi.org\/10.1109\/hpcs48598.2019.9188056","relation":{},"subject":[],"published":{"date-parts":[[2019,7]]}}}