{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,29]],"date-time":"2024-10-29T18:06:34Z","timestamp":1730225194781,"version":"3.28.0"},"reference-count":30,"publisher":"IEEE","license":[{"start":{"date-parts":[[2019,7,1]],"date-time":"2019-07-01T00:00:00Z","timestamp":1561939200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2019,7,1]],"date-time":"2019-07-01T00:00:00Z","timestamp":1561939200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2019,7,1]],"date-time":"2019-07-01T00:00:00Z","timestamp":1561939200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2019,7]]},"DOI":"10.1109\/hpcs48598.2019.9188138","type":"proceedings-article","created":{"date-parts":[[2020,9,9]],"date-time":"2020-09-09T20:58:33Z","timestamp":1599685113000},"page":"658-665","source":"Crossref","is-referenced-by-count":2,"title":["Exploration of Clustering Algorithms effects on Mesh of Clusters based FPGA Architecture Performance"],"prefix":"10.1109","author":[{"given":"Khouloud","family":"Bouaziz","sequence":"first","affiliation":[]},{"given":"Sonda","family":"Chtourou","sequence":"additional","affiliation":[]},{"given":"Zied","family":"Marrakchi","sequence":"additional","affiliation":[]},{"given":"Mohamed","family":"Abid","sequence":"additional","affiliation":[]},{"given":"Abdulfattah","family":"Obeid","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"journal-title":"Logic Synthesis and Optimization Benchmarks Version 3 0","year":"1991","author":"yang","key":"ref30"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1155\/2000\/19436"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1142\/S0218126604001222"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2007.4380635"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/2024724.2024908"},{"key":"ref14","article-title":"A novel multi-objective optimisation algorithm for routability and timing driven circuit clustering on fpgas","author":"wang","year":"2018","journal-title":"IET Computers and Digital Techniques"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-16214-0_37"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1155\/2009\/259837"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1145\/1117201.1117216"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2010.31"},{"journal-title":"ABC A System for Sequential Synthesis and Verification","year":"0","key":"ref19"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/92.748202"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1166\/jolpe.2005.023"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2004.824300"},{"key":"ref3","volume":"497","author":"betz","year":"2012","journal-title":"Architecture and CAD for Deep-Submicron FPGAs"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/605440.605448"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/43.712098"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/HPCS.2017.91"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/296399.296426"},{"key":"ref7","first-page":"551","article-title":"Cluster-based logic blocks for fpgas: Area-efficiency vs. input sharing and size","author":"betz","year":"1997","journal-title":"Custom Integrated Circuits Conference 1997 Proceedings of the IEEE 1997"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/871506.871541"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/370155.370567"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.884574"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/EDTC.1995.470419"},{"journal-title":"Introduction to Algorithms","year":"2009","author":"cormen","key":"ref22"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1016\/B978-012370522-8.50024-8"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1016\/j.micpro.2015.11.011"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2006.311199"},{"journal-title":"CMOS VLSI Design A Circuits and Systems Perspective","year":"2015","author":"weste","key":"ref26"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2012.6412139"}],"event":{"name":"2019 International Conference on High Performance Computing & Simulation (HPCS)","start":{"date-parts":[[2019,7,15]]},"location":"Dublin, Ireland","end":{"date-parts":[[2019,7,19]]}},"container-title":["2019 International Conference on High Performance Computing & Simulation (HPCS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9183768\/9188050\/09188138.pdf?arnumber=9188138","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,7,17]],"date-time":"2022-07-17T21:49:06Z","timestamp":1658094546000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9188138\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,7]]},"references-count":30,"URL":"https:\/\/doi.org\/10.1109\/hpcs48598.2019.9188138","relation":{},"subject":[],"published":{"date-parts":[[2019,7]]}}}