{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,23]],"date-time":"2024-10-23T09:41:15Z","timestamp":1729676475381,"version":"3.28.0"},"reference-count":14,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2011,7]]},"DOI":"10.1109\/hpcsim.2011.5999833","type":"proceedings-article","created":{"date-parts":[[2011,8,31]],"date-time":"2011-08-31T19:18:55Z","timestamp":1314818335000},"page":"264-272","source":"Crossref","is-referenced-by-count":1,"title":["Software prefetch on core micro-architecture applied to irregular codes"],"prefix":"10.1109","author":[{"given":"Samir","family":"Ammenouche","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"David E.","family":"Singh","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jesus","family":"Carretero","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"William","family":"Jalby","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"journal-title":"University of Florida Sparse Matrix Collection Sparse Matrices from a Wide Range of Applications","year":"2010","author":"davis","key":"13"},{"journal-title":"Optimizing application performance on Intel Core microarchitecture using hardware-implemented prefetchers","year":"2008","key":"14"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1147\/rd.416.0711"},{"key":"12","article-title":"The speedup-test","author":"touati","year":"2010","journal-title":"Tech Rep University of Versailles Saint-quentin en Yvelines"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1016\/S0167-8191(01)00089-8"},{"journal-title":"Intel VTune","year":"0","key":"2"},{"journal-title":"Sparskit A Basic Tool Kit for Sparse Matrix Computations - Version 2","year":"1994","author":"saad","key":"1"},{"key":"10","article-title":"Performance analysis of hardware prefetching units for irregular codes","author":"ammenouche","year":"2010","journal-title":"Technical Report"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/SUPERC.1992.236646"},{"key":"6","doi-asserted-by":"crossref","DOI":"10.1145\/331532.331562","article-title":"Improving performance of sparse matrix-vector multiplication","author":"pinar","year":"1999","journal-title":"Proc 1999 ACM\/IEEE Supercomputing Conf"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1137\/0713020"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/HPCC.2008.96"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1145\/1183401.1183444"},{"key":"8","doi-asserted-by":"crossref","first-page":"297","DOI":"10.1007\/s00200-007-0038-9","article-title":"When cache blocking sparse matrix vector multiply works and why","volume":"18","author":"nishtala","year":"2007","journal-title":"Appl Algebra Eng Commun Comput"}],"event":{"name":"Simulation (HPCS)","start":{"date-parts":[[2011,7,4]]},"location":"Istanbul, Turkey","end":{"date-parts":[[2011,7,8]]}},"container-title":["2011 International Conference on High Performance Computing & Simulation"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5979720\/5999789\/05999833.pdf?arnumber=5999833","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,20]],"date-time":"2017-06-20T05:27:40Z","timestamp":1497936460000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5999833\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,7]]},"references-count":14,"URL":"https:\/\/doi.org\/10.1109\/hpcsim.2011.5999833","relation":{},"subject":[],"published":{"date-parts":[[2011,7]]}}}