{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,9]],"date-time":"2026-01-09T14:39:48Z","timestamp":1767969588277,"version":"3.49.0"},"reference-count":24,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2012,7]]},"DOI":"10.1109\/hpcsim.2012.6266926","type":"proceedings-article","created":{"date-parts":[[2012,8,22]],"date-time":"2012-08-22T10:48:48Z","timestamp":1345632528000},"page":"288-294","source":"Crossref","is-referenced-by-count":7,"title":["An approach for customizing on-chip interconnect architectures in SoC design"],"prefix":"10.1109","author":[{"given":"A.","family":"Chariete","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"M.","family":"Bakhouya","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"J.","family":"Gaber","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"M.","family":"Wack","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"19","doi-asserted-by":"publisher","DOI":"10.1109\/SPL.2008.4547735"},{"key":"22","author":"lavina","year":"2007","journal-title":"A Simulator for NOC Interconnect Routing and Application Modeling[Z]"},{"key":"17","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2006.871762"},{"key":"23","first-page":"1","author":"suboh","year":"2010","journal-title":"Towards An Adaptive Interconnect for System-on-Chip"},{"key":"18","doi-asserted-by":"publisher","DOI":"10.1007\/s11235-008-9077-1"},{"key":"24","doi-asserted-by":"crossref","first-page":"387","DOI":"10.1016\/j.sysarc.2009.07.002","article-title":"Evaluating the Energy Consumption and the Silicon Area of On-Chip Interconnect Architectures","volume":"55","author":"bakhouya","year":"2009","journal-title":"Journal of Systems Architecture"},{"key":"15","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2003.1240887"},{"key":"16","doi-asserted-by":"publisher","DOI":"10.1109\/ICVD.2005.113"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2006.878263"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2005.134"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1145\/1084834.1084856"},{"key":"12","article-title":"Application-specific network-onchip architecture customization via long-range link insertion","author":"ogras","year":"0","journal-title":"Proc ICC 2005"},{"key":"21","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2000.840047"},{"key":"3","article-title":"Simulation and analysis of network on ship architectures: Ring, spidergon, and 2D mesh","author":"bononi","year":"0","journal-title":"Proc DATE 2006"},{"key":"20","doi-asserted-by":"publisher","DOI":"10.1145\/1151074.1151076"},{"key":"2","doi-asserted-by":"crossref","first-page":"105","DOI":"10.1016\/j.sysarc.2003.07.004","article-title":"Qnoc: Qos architecture and design process for network on chip","volume":"50","author":"bolotinand","year":"2004","journal-title":"Journal of Systems Architecture"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/2.976921"},{"key":"10","doi-asserted-by":"crossref","first-page":"384","DOI":"10.1016\/j.sysarc.2007.07.006","article-title":"Designing efficient irregular networks for heterogeneous systems-on-chip","volume":"54","author":"neeb","year":"2008","journal-title":"Journal of Systems Architecture"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1561\/1000000011"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2002.1016885"},{"key":"5","year":"2008","journal-title":"Cell Broadband Engine Programming Handbook"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/ISSOC.2004.1411133"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1016\/j.simpat.2010.10.008"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2007.900742"}],"event":{"name":"2012 International Conference on High Performance Computing & Simulation (HPCS)","location":"Madrid, Spain","start":{"date-parts":[[2012,7,2]]},"end":{"date-parts":[[2012,7,6]]}},"container-title":["2012 International Conference on High Performance Computing & Simulation (HPCS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/6260982\/6266874\/06266926.pdf?arnumber=6266926","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,20]],"date-time":"2017-06-20T19:09:10Z","timestamp":1497985750000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6266926\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,7]]},"references-count":24,"URL":"https:\/\/doi.org\/10.1109\/hpcsim.2012.6266926","relation":{},"subject":[],"published":{"date-parts":[[2012,7]]}}}