{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,29]],"date-time":"2025-09-29T11:49:09Z","timestamp":1759146549556,"version":"3.28.0"},"reference-count":17,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2013,7]]},"DOI":"10.1109\/hpcsim.2013.6641416","type":"proceedings-article","created":{"date-parts":[[2013,10,29]],"date-time":"2013-10-29T19:23:43Z","timestamp":1383074623000},"page":"213-216","source":"Crossref","is-referenced-by-count":2,"title":["FracNoC: A fractal on-chip interconnect architecture for System-on-Chip"],"prefix":"10.1109","author":[{"given":"A.","family":"Chariete","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"M.","family":"Bakhouya","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"J.","family":"Gaber","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"M.","family":"Wack","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"17","doi-asserted-by":"publisher","DOI":"10.1016\/1383-7621(96)88853-9"},{"key":"15","doi-asserted-by":"publisher","DOI":"10.1016\/j.physa.2007.07.069"},{"journal-title":"A Simulator for NoC Interconnect Routing and Application Modeling v1 1","year":"2007","author":"lavina","key":"16"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.2002.1012731"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1109\/MNET.2005.1509950"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/HPCSim.2012.6266926"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/IPPS.1999.760449"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.4018\/jertcs.2010040105"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1145\/378239.379048"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/2.976921"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2006.878263"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2005.134"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2000.840047"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/ISSOC.2004.1411133"},{"key":"4","first-page":"86","article-title":"Synthesis of predictable networks-on-chipbased interconnect architectures for chip multiprocessors","volume":"8","author":"murali","year":"2007","journal-title":"IEEE Transactions on VLSI Systems"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2002.1016885"},{"key":"8","first-page":"137","article-title":"An interconnection architecture for network-on-chip systems, telecommunication systems","volume":"37","author":"suboh","year":"2008","journal-title":"Springer"}],"event":{"name":"2013 International Conference on High Performance Computing & Simulation (HPCS)","start":{"date-parts":[[2013,7,1]]},"location":"Helsinki, Finland","end":{"date-parts":[[2013,7,5]]}},"container-title":["2013 International Conference on High Performance Computing &amp; Simulation (HPCS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6619547\/6641375\/06641416.pdf?arnumber=6641416","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,22]],"date-time":"2017-03-22T20:02:58Z","timestamp":1490212978000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6641416\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,7]]},"references-count":17,"URL":"https:\/\/doi.org\/10.1109\/hpcsim.2013.6641416","relation":{},"subject":[],"published":{"date-parts":[[2013,7]]}}}