{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,23]],"date-time":"2024-10-23T08:58:45Z","timestamp":1729673925129,"version":"3.28.0"},"reference-count":19,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2015,7]]},"DOI":"10.1109\/hpcsim.2015.7237030","type":"proceedings-article","created":{"date-parts":[[2015,9,3]],"date-time":"2015-09-03T17:45:56Z","timestamp":1441302356000},"page":"123-128","source":"Crossref","is-referenced-by-count":1,"title":["Analysis of asymmetric 3D DRAM architecture in combination with L2 cache size reduction"],"prefix":"10.1109","author":[{"given":"Alex","family":"Schoenberger","sequence":"first","affiliation":[]},{"given":"Klaus","family":"Hofmann","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/HPEC.2013.6670336"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/SC.2010.50"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2005.134"},{"key":"ref13","first-page":"33","article-title":"Cacti-3dd: Architecture-level modeling for 3d die-stacked dram main memory","author":"chen","year":"2012","journal-title":"Proceedings of the conference on Design Automation and Test in Europe"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2014.6974654"},{"year":"2006","key":"ref15","article-title":"DDR3 SDRAM MT41JXXXMX"},{"journal-title":"PLASMA","year":"2012","key":"ref16"},{"year":"0","key":"ref17","article-title":"Gcc. 4.9.0"},{"year":"0","key":"ref18","article-title":"bitmap"},{"year":"2000","key":"ref19","article-title":"Jpeg"},{"journal-title":"Computer Architecture A Quantitative Approach","year":"2012","author":"hennessy","key":"ref4"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ISSOC.2014.6972443"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/2429384.2429399"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2010.5416628"},{"key":"ref8","doi-asserted-by":"crossref","first-page":"453","DOI":"10.1145\/1394608.1382159","article-title":"3d-stacked memory architectures for multi-core processors","volume":"36","author":"loh","year":"2008","journal-title":"ACM SIGARCH Computer Architecture News"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2012.2235125"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/MECO.2014.6862663"},{"year":"0","key":"ref1","article-title":"2012, Nov) Openjpeg"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/3DIC.2013.6702348"}],"event":{"name":"2015 International Conference on High Performance Computing & Simulation (HPCS)","start":{"date-parts":[[2015,7,20]]},"location":"Amsterdam, Netherlands","end":{"date-parts":[[2015,7,24]]}},"container-title":["2015 International Conference on High Performance Computing &amp; Simulation (HPCS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7214433\/7237005\/07237030.pdf?arnumber=7237030","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,23]],"date-time":"2017-06-23T14:54:26Z","timestamp":1498229666000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7237030\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,7]]},"references-count":19,"URL":"https:\/\/doi.org\/10.1109\/hpcsim.2015.7237030","relation":{},"subject":[],"published":{"date-parts":[[2015,7]]}}}