{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,23]],"date-time":"2024-10-23T09:47:03Z","timestamp":1729676823274,"version":"3.28.0"},"reference-count":31,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2015,7]]},"DOI":"10.1109\/hpcsim.2015.7237059","type":"proceedings-article","created":{"date-parts":[[2015,9,3]],"date-time":"2015-09-03T21:45:56Z","timestamp":1441316756000},"page":"334-341","source":"Crossref","is-referenced-by-count":1,"title":["Performance evaluation of Data Mining algorithms on three generations of Intel<sup>®<\/sup> microarchitecture"],"prefix":"10.1109","author":[{"given":"Satish Kumar","family":"Sadasivam","sequence":"first","affiliation":[]},{"given":"S. Thamarai","family":"Selvi","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref31","first-page":"191","article-title":"Characterizing and subsetting big data workloads","author":"zhen","year":"2014","journal-title":"IISWC"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.9790\/0661-0633241"},{"key":"ref10","first-page":"48","article-title":"Characterizing the branch misprediction penalty","author":"stijn","year":"2006","journal-title":"ISPASS"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/2150976.2150982"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/MASCOTS.2005.77"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/BigData.2013.6691693"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC.2013.6704671"},{"key":"ref15","first-page":"245","article-title":"ISA-independent workload characterization and its implications for specialized architectures","author":"sophia shao","year":"2013","journal-title":"ISPASS"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2007.56"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2013.6522302"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/ETCS.2009.288"},{"year":"0","key":"ref19","article-title":"Perf Tool"},{"year":"0","key":"ref28","article-title":"Going Under the Hood with Intel's Next Generation Microarchitecture Codename Haswell"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC.2006.302743"},{"year":"0","key":"ref27","article-title":"First the Tick, Now the Tock:Intel® Microarchitecture (Nehalem)"},{"year":"0","key":"ref3","article-title":"SPEC Benchmarks"},{"key":"ref6","first-page":"61","article-title":"An Architectural Characterization Study of Data Mining and Bioinformatics Workloads","author":"berkin","year":"2006","journal-title":"IISWC"},{"key":"ref29","doi-asserted-by":"crossref","first-page":"6","DOI":"10.1109\/MM.2014.10","article-title":"Haswell: The Fourth-Generation Intel Core Processor","volume":"34","author":"per","year":"2014","journal-title":"IEEE Micro"},{"key":"ref5","article-title":"Performance characterization of data mining applications using MineBench","author":"zambreno","year":"2006","journal-title":"Proc Workshop Computer Architecture Evaluation Using Commercial Workloads"},{"key":"ref8","first-page":"112","article-title":"Comparative architectural characterization of SPEC CPU2000 and CPU2006 benchmarks on the Intel® CoreTM 2 Duo processor","author":"arun","year":"2008","journal-title":"ICSAMOS"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1998.694759"},{"year":"0","key":"ref2","article-title":"Transaction Processing Performance Council"},{"key":"ref9","first-page":"242","article-title":"Branch Behavior of a Commercial OLTP Workload on Intel IA32 Processors","author":"murali","year":"2002","journal-title":"ICCD"},{"year":"0","key":"ref1","article-title":"SPEC CPU2006"},{"journal-title":"GCC GNU Compiler Collection","article-title":"Free Software Foundation","year":"0","key":"ref20"},{"key":"ref22","article-title":"The microarchitecture of Intel, AMD and VIA CPUs, An optimization guide for assembly programmers and compiler makers","author":"fog","year":"0","journal-title":"Technical University of Denmark"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1145\/2322176.2322187"},{"year":"0","key":"ref24","article-title":"Intel 64 and IA-32 architectures optimization reference manual"},{"year":"0","key":"ref23","article-title":"Intel 64 and IA-32 architectures software developer's manual combined volumes: 1,2A,2B,2C,3A,3B and 3C"},{"journal-title":"Performance Analysis Guide for Intel® Core™ i7 Processor and Intel® Xeon™ 5500 processors","year":"0","author":"levinthal","key":"ref26"},{"year":"0","key":"ref25","article-title":"Pin - A Dynamic Binary Instrumentation Tool"}],"event":{"name":"2015 International Conference on High Performance Computing & Simulation (HPCS)","start":{"date-parts":[[2015,7,20]]},"location":"Amsterdam, Netherlands","end":{"date-parts":[[2015,7,24]]}},"container-title":["2015 International Conference on High Performance Computing & Simulation (HPCS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7214433\/7237005\/07237059.pdf?arnumber=7237059","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,23]],"date-time":"2017-06-23T18:54:27Z","timestamp":1498244067000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7237059\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,7]]},"references-count":31,"URL":"https:\/\/doi.org\/10.1109\/hpcsim.2015.7237059","relation":{},"subject":[],"published":{"date-parts":[[2015,7]]}}}