{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,6]],"date-time":"2024-09-06T15:51:14Z","timestamp":1725637874590},"reference-count":14,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2016,7]]},"DOI":"10.1109\/hpcsim.2016.7568324","type":"proceedings-article","created":{"date-parts":[[2016,9,15]],"date-time":"2016-09-15T16:53:29Z","timestamp":1473958409000},"page":"116-124","source":"Crossref","is-referenced-by-count":1,"title":["A Chip-level Redundant Threading (CRT) scheme for shared-memory protection"],"prefix":"10.1109","author":[{"given":"Erol","family":"Koser","sequence":"first","affiliation":[]},{"given":"Korbinian","family":"Berthold","sequence":"additional","affiliation":[]},{"given":"Ravi","family":"Kumar Pujari","sequence":"additional","affiliation":[]},{"given":"Walter","family":"Stechele","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2007.100"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/L-CA.2008.12"},{"key":"ref12","article-title":"Adapting dynamic core coupling to a direct-network environment","author":"s\u00e1nchez","year":"2008","journal-title":"Proc XIX lornadas de Parale lismo"},{"key":"ref13","article-title":"GRUB IP core users manual","author":"gaisler","year":"2007","journal-title":"Gaisler Research"},{"journal-title":"Stanford baby benchmark suite","year":"0","author":"hennessy","key":"ref14"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/378995.379247"},{"key":"ref3","first-page":"401","article-title":"Error detection mechanisms for massively parallel multiprocessors","author":"cin","year":"1993","journal-title":"Proc Euromicro Workshop Parallel and Distributed Processing"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2002.1003565"},{"key":"ref5","first-page":"25","article-title":"Transient fault detection via simultaneous multithreading","author":"reinhardt","year":"2000","journal-title":"Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat No RS00201) ISCA"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/PRDC.2008.40"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/545214.545227"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/40.755464"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2005.69"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2003.1261390"}],"event":{"name":"2016 International Conference on High Performance Computing & Simulation (HPCS)","start":{"date-parts":[[2016,7,18]]},"location":"Innsbruck, Austria","end":{"date-parts":[[2016,7,22]]}},"container-title":["2016 International Conference on High Performance Computing &amp; Simulation (HPCS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7562293\/7568299\/07568324.pdf?arnumber=7568324","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2016,10,5]],"date-time":"2016-10-05T08:15:19Z","timestamp":1475655319000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7568324\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,7]]},"references-count":14,"URL":"https:\/\/doi.org\/10.1109\/hpcsim.2016.7568324","relation":{},"subject":[],"published":{"date-parts":[[2016,7]]}}}