{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,22]],"date-time":"2024-10-22T18:38:09Z","timestamp":1729622289104,"version":"3.28.0"},"reference-count":31,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2016,7]]},"DOI":"10.1109\/hpcsim.2016.7568328","type":"proceedings-article","created":{"date-parts":[[2016,9,15]],"date-time":"2016-09-15T20:53:29Z","timestamp":1473972809000},"page":"140-147","source":"Crossref","is-referenced-by-count":1,"title":["Adaptive allocation of default router paths in Network-on-Chips for latency reduction"],"prefix":"10.1109","author":[{"given":"Jan Moritz","family":"Joseph","sequence":"first","affiliation":[]},{"given":"Chritopher","family":"Blochwitz","sequence":"additional","affiliation":[]},{"given":"Thilo","family":"Pionteck","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref31","article-title":"Mapping of mpeg-4 decoding on a flexible architecture platform","author":"van der tol","year":"2002","journal-title":"Media Processors"},{"journal-title":"Principles and Practices of Interconnection Networks","year":"2004","author":"dally","key":"ref30"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/NORCHIP.2010.5669432"},{"key":"ref11","article-title":"Benchmarking modern multiprocessors","author":"bienia","year":"2011","journal-title":"Princeton University"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2005.22"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1049\/iet-cdt.2008.0093"},{"key":"ref14","doi-asserted-by":"crossref","first-page":"333","DOI":"10.1109\/MICRO.2006.50","article-title":"Vichar: A dynamic virtual channel regulator for network-on-chip routers","author":"nicopoulos","year":"2006","journal-title":"Microarchitecture 2006 MICRO-39 39th Annual IEEE\/ACM International Symposium"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2005.99"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1016\/j.sysarc.2003.07.004"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/NOCS.2007.10"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2008.76"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2010.5647666"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/ISSOC.2014.6972440"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/1250662.1250681"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2011.49"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2007.900725"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2010.5681443"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/HPCSim.2013.6641419"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2006.878263"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/CADS.2010.5623552"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1016\/j.sysarc.2012.10.004"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2005.134"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/EmbeddedCom-ScalCom.2009.57"},{"key":"ref1","first-page":"105","article-title":"A network on chip architecture and design methodology","author":"kumar","year":"2002","journal-title":"VLSI 2002 Proceedings IEEE Computer Society Annual Symposium on"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.7873\/DATE.2013.080"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/NOCS.2012.9"},{"key":"ref21","first-page":"1","article-title":"A lightweight early arbitration method for low-latency asynchronous 2d-mesh noc's","volume":"203","author":"jiang","year":"2015","journal-title":"Proceedings of the 52nd Annual Design Automation Conference"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1145\/2024716.2024718"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/L-CA.2007.2"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/ISSOC.2011.6089221"},{"key":"ref25","article-title":"Netrace: Dependency-tracking traces for efficient network-on-chip experimentation","author":"hestness","year":"2011","journal-title":"The University of Texas at Austin Department of Computer Science Tech Rep"}],"event":{"name":"2016 International Conference on High Performance Computing & Simulation (HPCS)","start":{"date-parts":[[2016,7,18]]},"location":"Innsbruck, Austria","end":{"date-parts":[[2016,7,22]]}},"container-title":["2016 International Conference on High Performance Computing &amp; Simulation (HPCS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7562293\/7568299\/07568328.pdf?arnumber=7568328","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,24]],"date-time":"2017-06-24T22:53:40Z","timestamp":1498344820000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7568328\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,7]]},"references-count":31,"URL":"https:\/\/doi.org\/10.1109\/hpcsim.2016.7568328","relation":{},"subject":[],"published":{"date-parts":[[2016,7]]}}}