{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,3]],"date-time":"2024-09-03T20:34:05Z","timestamp":1725395645097},"reference-count":16,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2016,7]]},"DOI":"10.1109\/hpcsim.2016.7568336","type":"proceedings-article","created":{"date-parts":[[2016,9,15]],"date-time":"2016-09-15T16:53:29Z","timestamp":1473958409000},"page":"204-212","source":"Crossref","is-referenced-by-count":1,"title":["Allocation of last level cache partitions through thread classification with parallel universes"],"prefix":"10.1109","author":[{"given":"Burak Sezin","family":"Ovant","sequence":"first","affiliation":[]},{"given":"Isa Ahmet","family":"Guney","sequence":"additional","affiliation":[]},{"given":"Muhammed Emin","family":"Savas","sequence":"additional","affiliation":[]},{"given":"Gurhan","family":"Kucuk","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/1454115.1454145"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2012.43"},{"key":"ref12","article-title":"Talus: A Simple Way to Remove Cliffs in Cache Performance","author":"nathan","year":"2015","journal-title":"Proc HPCA-"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2012.6237037"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/2597652.2597653"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2014.46"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2015.7056026"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-20119-1_29"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2012.19"},{"article-title":"Instruction tables lists of instruction latencies, throughputs and micro operation breakdowns for Intel, AMD and VIA CPUs, Copenhagen University College of Engineering","year":"0","author":"fog","key":"ref6"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/1250662.1250709"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2001.953283"},{"year":"0","key":"ref7","article-title":"Macsim simulator"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/1555815.1555778"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.49"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/L-CA.2011.1"}],"event":{"name":"2016 International Conference on High Performance Computing & Simulation (HPCS)","start":{"date-parts":[[2016,7,18]]},"location":"Innsbruck, Austria","end":{"date-parts":[[2016,7,22]]}},"container-title":["2016 International Conference on High Performance Computing & Simulation (HPCS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7562293\/7568299\/07568336.pdf?arnumber=7568336","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2016,10,5]],"date-time":"2016-10-05T07:55:24Z","timestamp":1475654124000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7568336\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,7]]},"references-count":16,"URL":"https:\/\/doi.org\/10.1109\/hpcsim.2016.7568336","relation":{},"subject":[],"published":{"date-parts":[[2016,7]]}}}