{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,8]],"date-time":"2024-09-08T14:05:32Z","timestamp":1725804332965},"reference-count":32,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2016,7]]},"DOI":"10.1109\/hpcsim.2016.7568358","type":"proceedings-article","created":{"date-parts":[[2016,9,15]],"date-time":"2016-09-15T20:53:29Z","timestamp":1473972809000},"page":"364-371","source":"Crossref","is-referenced-by-count":1,"title":["Optimising simulation data structures for the Xeon Phi"],"prefix":"10.1109","author":[{"given":"Mozhgan K.","family":"Chimeh","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Paul","family":"Cockshott","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"doi-asserted-by":"publisher","key":"ref32","DOI":"10.1109\/TCAD.2002.800456"},{"year":"0","author":"synthesis","journal-title":"Berkeley Logic Interchange Format (BLIF)","key":"ref31"},{"doi-asserted-by":"publisher","key":"ref30","DOI":"10.1109\/ISPDC.2010.26"},{"doi-asserted-by":"publisher","key":"ref10","DOI":"10.1109\/DATE.2009.5090871"},{"doi-asserted-by":"publisher","key":"ref11","DOI":"10.1145\/1970353.1970363"},{"doi-asserted-by":"publisher","key":"ref12","DOI":"10.1007\/s10766-011-0164-7"},{"key":"ref13","first-page":"608","article-title":"Logic simulation acceleration based on GPU","author":"yuxuan","year":"2011","journal-title":"Mixed Design of Integrated Circuits and Systems (MIXDES) 2011 Proceedings of the 18th InternationalConference"},{"key":"ref14","article-title":"Yapsim: Yet another parallel logic simulator using gp-gpu","author":"hashiguchi","year":"2015","journal-title":"The 19th Workshop on Synthesis And System Integration of Mixed Information technologies SASIMI 2015"},{"doi-asserted-by":"publisher","key":"ref15","DOI":"10.1007\/978-3-642-14295-6_5"},{"doi-asserted-by":"publisher","key":"ref16","DOI":"10.1145\/1723112.1723144"},{"doi-asserted-by":"publisher","key":"ref17","DOI":"10.1145\/1146909.1147048"},{"doi-asserted-by":"publisher","key":"ref18","DOI":"10.1109\/DAC.2006.229206"},{"doi-asserted-by":"publisher","key":"ref19","DOI":"10.1109\/ICCAD.2005.1560122"},{"year":"2012","author":"reinders","journal-title":"An Overview of Programming for Intel Xeon Processors and Intel Xeon Phi Coprocessors","key":"ref28"},{"doi-asserted-by":"publisher","key":"ref4","DOI":"10.1109\/DAC.1988.14753"},{"doi-asserted-by":"publisher","key":"ref27","DOI":"10.1109\/TPDS.2013.193"},{"key":"ref3","article-title":"A survey on parallel logic simulation","author":"meister","year":"1993","journal-title":"Technical report University of Saarland Department of Computer Science Misra J"},{"doi-asserted-by":"publisher","key":"ref6","DOI":"10.1109\/EDAC.1992.205898"},{"doi-asserted-by":"publisher","key":"ref29","DOI":"10.1002\/cpe.3509"},{"doi-asserted-by":"publisher","key":"ref5","DOI":"10.1049\/ip-cds:19960477"},{"doi-asserted-by":"publisher","key":"ref8","DOI":"10.1109\/IPPS.1994.288193"},{"doi-asserted-by":"publisher","key":"ref7","DOI":"10.1145\/174134.158469"},{"doi-asserted-by":"publisher","key":"ref2","DOI":"10.1145\/1629911.1630056"},{"year":"2007","author":"perinkulam","article-title":"Logic Simulation using Graphics Processors","key":"ref9"},{"doi-asserted-by":"publisher","key":"ref1","DOI":"10.1109\/MASCOTS.2012.24"},{"doi-asserted-by":"publisher","key":"ref20","DOI":"10.1109\/PADS.2000.847144"},{"key":"ref22","doi-asserted-by":"crossref","first-page":"94","DOI":"10.1109\/ICCSE.2012.23","article-title":"Optimisation and parallelism in synchronous digital circuit simulators","author":"chimeh","year":"2012","journal-title":"Computational Science and Engineering (CSE) 2012 IEEE 15th International Conference"},{"doi-asserted-by":"publisher","key":"ref21","DOI":"10.1145\/3916.3988"},{"doi-asserted-by":"publisher","key":"ref24","DOI":"10.1145\/1391469.1391679"},{"doi-asserted-by":"publisher","key":"ref23","DOI":"10.1145\/1970353.1970362"},{"doi-asserted-by":"publisher","key":"ref26","DOI":"10.1145\/1837274.1837369"},{"doi-asserted-by":"publisher","key":"ref25","DOI":"10.1109\/ATS.2010.12"}],"event":{"name":"2016 International Conference on High Performance Computing & Simulation (HPCS)","start":{"date-parts":[[2016,7,18]]},"location":"Innsbruck, Austria","end":{"date-parts":[[2016,7,22]]}},"container-title":["2016 International Conference on High Performance Computing & Simulation (HPCS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7562293\/7568299\/07568358.pdf?arnumber=7568358","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,9,13]],"date-time":"2019-09-13T15:13:19Z","timestamp":1568387599000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7568358\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,7]]},"references-count":32,"URL":"https:\/\/doi.org\/10.1109\/hpcsim.2016.7568358","relation":{},"subject":[],"published":{"date-parts":[[2016,7]]}}}