{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,12,6]],"date-time":"2025-12-06T04:58:05Z","timestamp":1764997085953,"version":"3.28.0"},"reference-count":18,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2016,7]]},"DOI":"10.1109\/hpcsim.2016.7568425","type":"proceedings-article","created":{"date-parts":[[2016,9,15]],"date-time":"2016-09-15T16:53:29Z","timestamp":1473958409000},"page":"866-874","source":"Crossref","is-referenced-by-count":4,"title":["A cache memory with unit tile and line accessibility"],"prefix":"10.1109","author":[{"given":"BaoKang","family":"Wang","sequence":"first","affiliation":[]},{"given":"Yuki","family":"Fukazawa","sequence":"additional","affiliation":[]},{"given":"Toshio","family":"Kondo","sequence":"additional","affiliation":[]},{"given":"Takahiro","family":"Sasaki","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1023\/A:1011119519789"},{"key":"ref11","article-title":"The effect of reordering multi-dimensional array data on CPU cache utilization","author":"ghane","year":"2013","journal-title":"SIMON FRASER UNIVERSITY"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/379539.379559"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPSW.2014.93"},{"key":"ref14","article-title":"Recursive Blocked Algorithms, Data Structures, and High- Performance Software for Solving Linear Systems and Matrix Equations","author":"jonsson","year":"2003","journal-title":"UMEA Universitv"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/223428.207162"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TCSVT.2015.2389472"},{"key":"ref17","first-page":"1031","article-title":"SIMD-based Datapath with Efficient Operation Structure","author":"fukazawa","year":"2016","journal-title":"IEEE Proc Of ICASSP"},{"year":"0","key":"ref18"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1007\/11752578_131"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/305619.305645"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1007\/BF01212412"},{"key":"ref5","first-page":"241","article-title":"Improving the performance of morton layout by array alignment and loop unrolling","volume":"2958","author":"thiyagalingam","year":"2003","journal-title":"International Workshops LNCS"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1002\/cpe.1018"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1504\/IJHPCN.2005.009429"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/106975.106981"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2003.1214317"},{"key":"ref9","article-title":"Improving cache locality with blocked array lavouts","author":"athanasaki","year":"2004","journal-title":"Proc Euromicro Int Conf on PDP"}],"event":{"name":"2016 International Conference on High Performance Computing & Simulation (HPCS)","start":{"date-parts":[[2016,7,18]]},"location":"Innsbruck, Austria","end":{"date-parts":[[2016,7,22]]}},"container-title":["2016 International Conference on High Performance Computing &amp; Simulation (HPCS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7562293\/7568299\/07568425.pdf?arnumber=7568425","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2016,10,5]],"date-time":"2016-10-05T08:01:57Z","timestamp":1475654517000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7568425\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,7]]},"references-count":18,"URL":"https:\/\/doi.org\/10.1109\/hpcsim.2016.7568425","relation":{},"subject":[],"published":{"date-parts":[[2016,7]]}}}