{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,29]],"date-time":"2024-10-29T18:12:37Z","timestamp":1730225557418,"version":"3.28.0"},"reference-count":37,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2014,9]]},"DOI":"10.1109\/hpec.2014.7040951","type":"proceedings-article","created":{"date-parts":[[2015,2,17]],"date-time":"2015-02-17T19:50:25Z","timestamp":1424202625000},"page":"1-6","source":"Crossref","is-referenced-by-count":5,"title":["Performance and energy limits of a processor-integrated FFT accelerator"],"prefix":"10.1109","author":[{"given":"Tung","family":"Thanh-Hoang","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Amirali","family":"Shambayati","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Calvin","family":"Deutschbein","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Henry","family":"Hoffmann","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Andrew A.","family":"Chien","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"19","doi-asserted-by":"publisher","DOI":"10.1145\/1065579.1065703"},{"key":"35","doi-asserted-by":"publisher","DOI":"10.1109\/TCE.2011.5735479"},{"key":"17","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2008.15"},{"key":"36","doi-asserted-by":"publisher","DOI":"10.1109\/3DIC.2013.6702348"},{"journal-title":"FFT Implementation on the TMS320VC5505","year":"2013","author":"mckeown","key":"18"},{"key":"33","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2010.5416628"},{"key":"15","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2005.846667"},{"key":"34","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2012.2194315"},{"journal-title":"MIPS R2000 RISC Architecture","year":"1987","author":"kane","key":"16"},{"key":"13","article-title":"A reconfigurable application-specific instructionset processor for fast fourier transform processing","author":"hussain","year":"2013","journal-title":"ASAP"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.2012.6242474"},{"key":"37","doi-asserted-by":"publisher","DOI":"10.1109\/VLSISP.1996.558311"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2011.298"},{"key":"12","article-title":"A generalized mixed-radix algorithm for memory-based FFT processors","volume":"57","author":"hsiao","year":"2010","journal-title":"Circuits and Systems II Express Briefs IEEE Trans on"},{"key":"21","doi-asserted-by":"publisher","DOI":"10.1109\/SAMOS.2013.6621102"},{"key":"20","doi-asserted-by":"publisher","DOI":"10.1145\/2024724.2024954"},{"key":"22","article-title":"Hybrid memory cube (HMC)","volume":"23","author":"pawlowski","year":"2011","journal-title":"Hot Chips"},{"key":"23","doi-asserted-by":"publisher","DOI":"10.1109\/ASAP.2013.6567572"},{"key":"24","article-title":"Preliminary design review: GMTI processing for the PCA integrated radar-tracker application","author":"reuther","year":"2004","journal-title":"Tech Rep ESC-TR-2003-070 MIT Lincoln Laboratory"},{"key":"25","doi-asserted-by":"publisher","DOI":"10.1109\/SAMOS.2013.6621101"},{"key":"26","doi-asserted-by":"publisher","DOI":"10.1109\/L-CA.2011.4"},{"key":"27","doi-asserted-by":"publisher","DOI":"10.1109\/12.859540"},{"year":"0","key":"28"},{"key":"29","doi-asserted-by":"publisher","DOI":"10.1145\/1594233.1594289"},{"key":"3","article-title":"Single-chip heterogeneous computing: Does the future include custom logic, FPGAs, and GPGPUs?","author":"chung","year":"2010","journal-title":"Micro"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/SOCDC.2008.4815625"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.1998.694922"},{"key":"1","article-title":"Performance modeling of a UAV system with an integrated radar-tracker using petri nets","author":"amduka","year":"0","journal-title":"Tech Rep Lockheed Martin Advanced Technology Laboratories"},{"key":"30","doi-asserted-by":"publisher","DOI":"10.1145\/1394608.1382127"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1007\/s11265-008-0264-9"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/MSP.2009.934155"},{"key":"32","doi-asserted-by":"publisher","DOI":"10.1145\/1736020.1736044"},{"key":"5","first-page":"365","article-title":"Dark silicon and the end of multicore scaling","author":"esmaeilzadeh","year":"2011","journal-title":"2011 38th Annual International Symposium on Computer Architecture (ISCA) ISCA"},{"key":"31","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2013.6557174"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1090\/S0025-5718-1965-0178586-1"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2007170"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2010.12"}],"event":{"name":"2014 IEEE High Performance Extreme Computing Conference (HPEC)","start":{"date-parts":[[2014,9,9]]},"location":"Waltham, MA, USA","end":{"date-parts":[[2014,9,11]]}},"container-title":["2014 IEEE High Performance Extreme Computing Conference (HPEC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7027306\/7040940\/07040951.pdf?arnumber=7040951","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,24]],"date-time":"2017-03-24T03:39:25Z","timestamp":1490326765000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7040951\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,9]]},"references-count":37,"URL":"https:\/\/doi.org\/10.1109\/hpec.2014.7040951","relation":{},"subject":[],"published":{"date-parts":[[2014,9]]}}}