{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,12]],"date-time":"2026-03-12T08:31:12Z","timestamp":1773304272976,"version":"3.50.1"},"reference-count":10,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2014,9]]},"DOI":"10.1109\/hpec.2014.7040988","type":"proceedings-article","created":{"date-parts":[[2015,2,17]],"date-time":"2015-02-17T19:50:25Z","timestamp":1424202625000},"page":"1-6","source":"Crossref","is-referenced-by-count":71,"title":["An investigation of Unified Memory Access performance in CUDA"],"prefix":"10.1109","author":[{"given":"Raphael","family":"Landaverde","sequence":"first","affiliation":[]},{"family":"Tiansheng Zhang","sequence":"additional","affiliation":[]},{"given":"Ayse K.","family":"Coskun","sequence":"additional","affiliation":[]},{"given":"Martin","family":"Herbordt","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2008.4536351"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1145\/1513895.1513898"},{"key":"10","first-page":"354","article-title":"Reducing GPU offload latency via finegrained CPU-GPU synchronization","author":"lustig","year":"2013","journal-title":"Proceedings of IEEE International Symposium on High Performance Computer Architecture"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2008.31"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC.2009.5306797"},{"key":"6","year":"2014","journal-title":"Cuda"},{"key":"5","first-page":"13","article-title":"On the limits of GPU acceleration","author":"vuduc","year":"2010","journal-title":"Proceedings of the 2nd USENIX Conference on Hot Topics in Parallelism"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/JSTARS.2011.2132117"},{"key":"9","author":"che","year":"2014","journal-title":"Unified Memory in CUDA 6"},{"key":"8","year":"2012","journal-title":"Nvidia Kepler GK110 Architecture"}],"event":{"name":"2014 IEEE High Performance Extreme Computing Conference (HPEC)","location":"Waltham, MA, USA","start":{"date-parts":[[2014,9,9]]},"end":{"date-parts":[[2014,9,11]]}},"container-title":["2014 IEEE High Performance Extreme Computing Conference (HPEC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7027306\/7040940\/07040988.pdf?arnumber=7040988","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,24]],"date-time":"2017-03-24T03:44:01Z","timestamp":1490327041000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7040988\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,9]]},"references-count":10,"URL":"https:\/\/doi.org\/10.1109\/hpec.2014.7040988","relation":{},"subject":[],"published":{"date-parts":[[2014,9]]}}}