{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,22]],"date-time":"2024-10-22T17:20:54Z","timestamp":1729617654737,"version":"3.28.0"},"reference-count":20,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2014,9]]},"DOI":"10.1109\/hpec.2014.7040998","type":"proceedings-article","created":{"date-parts":[[2015,2,17]],"date-time":"2015-02-17T19:50:25Z","timestamp":1424202625000},"page":"1-6","source":"Crossref","is-referenced-by-count":2,"title":["Algorithm\/hardware co-optimized SAR image reconstruction with 3D-stacked logic in memory"],"prefix":"10.1109","author":[{"given":"Fazle","family":"Sadi","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Berkin","family":"Akin","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Doru T.","family":"Popovici","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"James C.","family":"Hoe","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Larry","family":"Pileggi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Franz","family":"Franchetti","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"journal-title":"DesignWare Library Synopsys","year":"0","key":"19"},{"journal-title":"HP Labs","year":"0","key":"17"},{"journal-title":"McPAT 1 0 HP Labs","year":"0","key":"18"},{"key":"15","doi-asserted-by":"publisher","DOI":"10.1109\/3DIC.2013.6702348"},{"key":"16","doi-asserted-by":"publisher","DOI":"10.1109\/ASAP.2014.6868669"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2012.40"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1109\/ICASSP.2014.6854332"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.2010.5556202"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/ASAP.2012.21"},{"key":"3","article-title":"Implementation of polar format sar image formation on the ibm cell broadband engine","author":"rudin","year":"0","journal-title":"High Performance Embedded Computing (HPEC)"},{"key":"20","first-page":"33","article-title":"CACTI-3DD: Architecture-level modeling for 3D die-stacked DRAM main memory","author":"chen","year":"2012","journal-title":"Proceedings of the Design Automation and Test in Europe (DATE)"},{"journal-title":"Spotlight-Mode Synthetic Aperture Radar A Signal Processing Approach","year":"0","author":"wahl","key":"2"},{"journal-title":"Spotlight Synthetic Aperture Radar Signal Processing Algorithms Ser Artech House Signal Processing Library","year":"0","author":"carrara","key":"1"},{"key":"10","first-page":"104","article-title":"Design of embedded memory and logic based on pattern constructs","author":"morris","year":"2011","journal-title":"Symposium on VLSI Technology (VLSIT)"},{"key":"7","first-page":"453","article-title":"3D-Stacked memory architectures for multi-core processors","author":"loh","year":"2008","journal-title":"35th International Symposium on Computer Architecture (ISCA)"},{"journal-title":"OMAP Applications Processor","year":"0","key":"6"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/HPEC.2012.6408665"},{"key":"4","doi-asserted-by":"crossref","DOI":"10.1117\/12.818399","article-title":"High performance synthetic aperture radar image formation on commodity multicore architectures","volume":"7337","author":"mcfarlin","year":"2009","journal-title":"SPIE Proceedings"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2004.840306"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/MWSCAS.2011.6026428"}],"event":{"name":"2014 IEEE High Performance Extreme Computing Conference (HPEC)","start":{"date-parts":[[2014,9,9]]},"location":"Waltham, MA, USA","end":{"date-parts":[[2014,9,11]]}},"container-title":["2014 IEEE High Performance Extreme Computing Conference (HPEC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7027306\/7040940\/07040998.pdf?arnumber=7040998","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,23]],"date-time":"2017-06-23T05:43:56Z","timestamp":1498196636000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7040998\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,9]]},"references-count":20,"URL":"https:\/\/doi.org\/10.1109\/hpec.2014.7040998","relation":{},"subject":[],"published":{"date-parts":[[2014,9]]}}}