{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,4,16]],"date-time":"2025-04-16T18:23:05Z","timestamp":1744827785247,"version":"3.28.0"},"reference-count":26,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2018,9]]},"DOI":"10.1109\/hpec.2018.8547561","type":"proceedings-article","created":{"date-parts":[[2018,12,7]],"date-time":"2018-12-07T19:50:56Z","timestamp":1544212256000},"page":"1-7","source":"Crossref","is-referenced-by-count":14,"title":["PageRank Acceleration for Large Graphs with Scalable Hardware and Two-Step SpMV"],"prefix":"10.1109","author":[{"given":"Fazle","family":"Sadi","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Joe","family":"Sweeney","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Scott","family":"McMillan","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Tze Meng","family":"Low","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"James C.","family":"Hoe","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Larry","family":"Pileggi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Franz","family":"Franchetti","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.14778\/1938545.1938548"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/HIPC.1997.634472"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/IMW.2017.7939084"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/HPEC.2017.8091096"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2008.4536313"},{"key":"ref15","doi-asserted-by":"crossref","first-page":"711","DOI":"10.1147\/rd.416.0711","article-title":"Improving memory-system performance of sparse matrix-vector multiplication","volume":"41","author":"toledo","year":"1997","journal-title":"IBM Journal of Research and Development"},{"key":"ref16","first-page":"104","article-title":"Design of embedded memory and logic based on pattern constructs","author":"morris","year":"2011","journal-title":"Symposium on VLSI Technology (VLSIT)"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ASAP.2012.21"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.2010.5556202"},{"key":"ref19","first-page":"33","article-title":"CACTI-3DD: Architecture-level modeling for 3D die-stacked DRAM main memory","author":"chen","year":"2012","journal-title":"Proceedings of the Design Automation and Test in Europe (DATE)"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2016.7783759"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ReConFig.2015.7393332"},{"key":"ref6","volume":"abs 1709 7122","author":"lakhotia","year":"2017","journal-title":"Accelerating pagerank using partition-centric processing"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/HPEC.2017.8091048"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/1654059.1654078"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1016\/j.parco.2008.12.006"},{"key":"ref2","first-page":"14","article-title":"Scalability! but at what cost?","author":"mcsherry","year":"2015","journal-title":"Proceedings of the 13th USENIX Conference on Hot Topics in Operating Systems"},{"key":"ref9","doi-asserted-by":"crossref","first-page":"115","DOI":"10.1145\/1837853.1693471","article-title":"Model-driven autotuning of sparse matrix-vector multiply on gpus","volume":"45","author":"choi","year":"2010","journal-title":"SIGPLAN Not"},{"key":"ref1","volume":"abs 1603 1876","author":"dreher","year":"2016","journal-title":"PageRank Pipeline Benchmark Proposal for a Holistic System Benchmark for Big-Data Platforms"},{"key":"ref20","first-page":"1543","article-title":"Destiny: A tool for modeling emerging 3d nvm and edram caches","author":"poremba","year":"2015","journal-title":"Design Automation Test in Europe Conference Exhibition (DATE) 2015"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/EDAPS.2015.7383697"},{"key":"ref21","article-title":"High bandwidth memory (hbm) dram","author":"standard","year":"2013","journal-title":"JESD235"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1561\/106.00000003"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1145\/2487788.2488173"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1145\/1772690.1772751"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1145\/2049662.2049663"}],"event":{"name":"2018 IEEE High Performance Extreme Computing Conference (HPEC)","start":{"date-parts":[[2018,9,25]]},"location":"Waltham, MA","end":{"date-parts":[[2018,9,27]]}},"container-title":["2018 IEEE High Performance extreme Computing Conference (HPEC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8534508\/8547513\/08547561.pdf?arnumber=8547561","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,8,23]],"date-time":"2020-08-23T23:47:41Z","timestamp":1598226461000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8547561\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,9]]},"references-count":26,"URL":"https:\/\/doi.org\/10.1109\/hpec.2018.8547561","relation":{},"subject":[],"published":{"date-parts":[[2018,9]]}}}