{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T01:03:49Z","timestamp":1740099829528,"version":"3.37.3"},"reference-count":18,"publisher":"IEEE","license":[{"start":{"date-parts":[[2020,9,22]],"date-time":"2020-09-22T00:00:00Z","timestamp":1600732800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2020,9,22]],"date-time":"2020-09-22T00:00:00Z","timestamp":1600732800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2020,9,22]],"date-time":"2020-09-22T00:00:00Z","timestamp":1600732800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/100000001","name":"National Science Foundation","doi-asserted-by":"publisher","award":["A#: 1764000"],"award-info":[{"award-number":["A#: 1764000"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000015","name":"Department of Energy (DOE)","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100000015","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100006370","name":"Small Business Innovation Research (SBIR) ASCR Program","doi-asserted-by":"publisher","award":["DE-SC0017182"],"award-info":[{"award-number":["DE-SC0017182"]}],"id":[{"id":"10.13039\/100006370","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2020,9,22]]},"DOI":"10.1109\/hpec43674.2020.9286162","type":"proceedings-article","created":{"date-parts":[[2020,12,22]],"date-time":"2020-12-22T21:07:15Z","timestamp":1608671235000},"page":"1-6","source":"Crossref","is-referenced-by-count":1,"title":["A Scalable Architecture for CNN Accelerators Leveraging High-Performance Memories"],"prefix":"10.1109","author":[{"given":"Maarten","family":"Hattink","sequence":"first","affiliation":[]},{"given":"Giuseppe","family":"Di Guglielmo","sequence":"additional","affiliation":[]},{"given":"Luca P.","family":"Carloni","sequence":"additional","affiliation":[]},{"given":"Keren","family":"Bergman","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"journal-title":"Inc Micron Technology Hybrid Memory Cube - HMC Gen2","year":"0","key":"ref10"},{"journal-title":"Xilinx Inc AXI High Bandwidth Memory Controller v1 0","year":"0","key":"ref11"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1137\/1.9781611970364"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2015.2480849"},{"journal-title":"Micron Technology Inc AC-510","year":"0","key":"ref14"},{"journal-title":"Very Deep Convolutional Networks for Large-scale Image Recognition","year":"2014","author":"simonyan","key":"ref15"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/3061639.3062208"},{"journal-title":"Xilinx Inc UltraScale Architecture-Based FPGAs Memory IP vl 4","year":"0","key":"ref17"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2016.7428012"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.23919\/DATE48585.2020.9116317"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/3186332"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.23919\/FPL.2017.8056824"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/2684746.2689060"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1088\/1742-6596\/1026\/1\/012019"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2016.435"},{"journal-title":"A Survey of FPGA Based Neural Network Accelerator","year":"2017","author":"guo","key":"ref2"},{"journal-title":"Accelerating CNN inference on FPGAs A survey","year":"2018","author":"abdelouahab","key":"ref1"},{"journal-title":"Xilinx Inc Memory Solutions - External Memory Interfaces","year":"0","key":"ref9"}],"event":{"name":"2020 IEEE High Performance Extreme Computing Conference (HPEC)","start":{"date-parts":[[2020,9,22]]},"location":"Waltham, MA, USA","end":{"date-parts":[[2020,9,24]]}},"container-title":["2020 IEEE High Performance Extreme Computing Conference (HPEC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9285977\/9286137\/09286162.pdf?arnumber=9286162","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,6,27]],"date-time":"2022-06-27T15:54:47Z","timestamp":1656345287000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9286162\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,9,22]]},"references-count":18,"URL":"https:\/\/doi.org\/10.1109\/hpec43674.2020.9286162","relation":{},"subject":[],"published":{"date-parts":[[2020,9,22]]}}}