{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,29]],"date-time":"2024-10-29T18:17:12Z","timestamp":1730225832541,"version":"3.28.0"},"reference-count":66,"publisher":"IEEE","license":[{"start":{"date-parts":[[2023,9,25]],"date-time":"2023-09-25T00:00:00Z","timestamp":1695600000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2023,9,25]],"date-time":"2023-09-25T00:00:00Z","timestamp":1695600000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2023,9,25]]},"DOI":"10.1109\/hpec58863.2023.10363509","type":"proceedings-article","created":{"date-parts":[[2023,12,25]],"date-time":"2023-12-25T14:39:57Z","timestamp":1703515197000},"page":"1-8","source":"Crossref","is-referenced-by-count":0,"title":["Pruning Binarized Neural Networks Enables Low-Latency, Low-Power FPGA-Based Handwritten Digit Classification"],"prefix":"10.1109","author":[{"given":"Syamantak","family":"Payra","sequence":"first","affiliation":[{"name":"Stanford University (formerly Dept. of Electrical Engineering and Computer Science, Massachusetts Institute of Technology),Dept. of Electrical Engineering"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Gabriel","family":"Loke","sequence":"additional","affiliation":[{"name":"Massachusetts Institute of Technology,Dept. of Materials Science and Engineering"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yoel","family":"Fink","sequence":"additional","affiliation":[{"name":"Massachusetts Institute of Technology,Dept. of Materials Science and Engineering, Dept. of Electrical Engineering and Computer Science, and Institute for Soldier Nanotechnologies"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Joseph D.","family":"Steinmeyer","sequence":"additional","affiliation":[{"name":"Massachusetts Institute of Technology,Dept. of Electrical Enigneering and Computer Science"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"volume-title":"Convolutional Neural Networks at Constrained Time Cost","year":"2014","author":"He","key":"ref1"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/access.2018.2890150"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.3390\/jimaging5050053"},{"key":"ref4","article-title":"A COST-PERFORMANCE ANALYSIS OF EMBEDDED SYSTEMS FOR LOW AND MEDIUM-VOLUMES APPLICATIONS","volume-title":"Technical University of Moldova","author":"Secrieru","year":"2012"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.3390\/jimaging5010016"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/s3s.2017.8308753"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/MWSCAS.2019.8884910"},{"issue":"5","key":"ref8","first-page":"623","article-title":"Design and Implementation of Logic Gates and Adder Circuits on FPGA Using ANN","volume":"4","author":"Farha","year":"2016","journal-title":"Int. J. Res. Appl. Sci. Eng. Technol. Ijraset"},{"key":"ref9","article-title":"Architecture Design for Highly Flexible and Energy-Efficient Deep Neural Network Accelerators","author":"Chen","year":"2018","journal-title":"Massachusetts Institute of Technology"},{"volume-title":"Eyeriss v2: A Flexible Accelerator for Emerging Deep Neural Networks on Mobile Devices","year":"2019","author":"Chen","key":"ref10"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.3390\/jimaging5010007"},{"key":"ref12","article-title":"FPGA implementations of neural networks","volume-title":"Dordrecht","author":"Ormondi","year":"2006"},{"issue":"3","key":"ref13","first-page":"99","article-title":"Implementation of FPGA-Based General Purpose Artificial Neural Network","volume":"1","author":"Kalbande","year":"2013","journal-title":"ITSI Trans. Electr. Electron. Eng."},{"volume-title":"A General Neural Network Hardware Architecture on FPGA","year":"2017","author":"Hao","key":"ref14"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.15598\/aeee.v12i1.831"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/isss.2000.874054"},{"key":"ref17","article-title":"An FPGA Implementation for Convolutional Neural Network","volume-title":"Pontifical Catholic University of Rio Grande Do Sul","author":"Korol","year":"2019"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/iccvw.2009.5457611"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1088\/1748-0221\/13\/07\/P07027"},{"key":"ref20","article-title":"The Design and Implementation of Low-Latency Prediction Serving Systems","volume-title":"University of California at Berkeley, UCB\/EECS-2019\u2013171","author":"Crankshaw","year":"2019"},{"volume-title":"Freely scalable and reconfigurable optical hardware for deep learning","year":"2020","author":"Bernstein","key":"ref21"},{"key":"ref22","first-page":"10","article-title":"CryptoNets: Applying Neural Networks to Encrypted Data with High Throughput and Accuracy","volume-title":"Proceedings of the 33rd International Conference on Machine Learning","volume":"48","author":"Dowlin","year":"2016"},{"key":"ref23","first-page":"10","article-title":"Low Latency Privacy Preserving Inference","volume-title":"Proceedings of the 36th International Conference on Machine Learning","volume":"97","author":"Brutzkus","year":"2019"},{"key":"ref24","first-page":"17","author":"Juvekar","year":"2018","journal-title":"GAZELLE: A Low Latency Framework for Secure Neural Network Inference"},{"volume-title":"A Survey of Model Compression and Acceleration for Deep Neural Networks","year":"2020","author":"Cheng","key":"ref25"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/tpami.2021.3089687"},{"key":"ref27","first-page":"8","article-title":"Rethinking floating point for deep learning","volume-title":"32nd Conference on Neural Information Processing Systems","author":"Johnson","year":"2018"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1145\/2684746.2689060"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1145\/2934583.2934644"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/ijcnn.2015.7280625"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/mce.2016.2590099"},{"volume-title":"A Channel-Pruned and Weight-Binarized Convolutional Neural Network for Keyword Spotting","year":"2019","author":"Lyu","key":"ref32"},{"key":"ref33","first-page":"9","article-title":"Binarized Neural Networks","volume-title":"30th Conference on Neural Information Processing Systems","author":"Hubara","year":"2016"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-46493-0_32"},{"volume-title":"The MNIST Database of Handwritten Digits","year":"1998","author":"LeCun","key":"ref35"},{"key":"ref36","first-page":"265","article-title":"TensorFlow: Large-Scale Machine Learning on Heterogeneous Distributed Systems","volume-title":"OSDI16","author":"Abadi","year":"2016"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1201\/b18401"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1038\/s41598-020-57866-2"},{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1162\/neco.1989.1.4.541"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/ccdc.2019.8832535"},{"volume-title":"Assessing four Neural Networks on Handwritten Digit Recognition Dataset (MNIST)","year":"2019","author":"Chen","key":"ref41"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.3390\/technologies8030046"},{"volume-title":"Automatic Pruning for Quantized Neural Networks","year":"2020","author":"Guerra","key":"ref43"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1109\/isqed48828.2020.9136977"},{"article-title":"Pruning Filters for Efficient ConvNets","volume-title":"presented at the International Conference on Learning Representations (ICLR)","author":"Li","key":"ref45"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1038\/s41586-018-0289-6"},{"volume-title":"NullaNet: Training Deep Neural Networks for Reduced-Memory-Access Inference","year":"2018","author":"Nazemi","key":"ref47"},{"article-title":"Bitwise Neural Networks","volume-title":"presented at the International Conference on Machine Learning (ICML) Workshop on Resource-Efficient Machine Learning","author":"Kim","key":"ref48"},{"key":"ref49","doi-asserted-by":"publisher","DOI":"10.1109\/ijcnn.2017.7966166"},{"key":"ref50","doi-asserted-by":"publisher","DOI":"10.1145\/3287624.3287722"},{"journal-title":"Towards Accurate Binary Convolutional Neural Network","first-page":"9","author":"Lin","key":"ref51"},{"key":"ref52","doi-asserted-by":"publisher","DOI":"10.5391\/ijfis.2018.18.2.126"},{"key":"ref53","doi-asserted-by":"publisher","DOI":"10.1145\/3020078.3021744"},{"key":"ref54","doi-asserted-by":"publisher","DOI":"10.18517\/ijaseit.9.1.6948"},{"key":"ref55","doi-asserted-by":"publisher","DOI":"10.1088\/2632-2153\/aba042"},{"key":"ref56","doi-asserted-by":"publisher","DOI":"10.1109\/access.2020.3047594"},{"key":"ref57","doi-asserted-by":"publisher","DOI":"10.1016\/j.neucom.2017.09.046"},{"journal-title":"A Digits-Recognition Convolutional Neural Network on FPGA","first-page":"45","author":"Wang","key":"ref58"},{"key":"ref59","doi-asserted-by":"publisher","DOI":"10.1146\/annurev-control-060117-105157"},{"key":"ref60","article-title":"How Many AA Batteries Would it Take to Power a Mercedes?","volume-title":"NSF Center for Sustainable Nanotechnology","author":"Krause","year":"2016"},{"key":"ref61","doi-asserted-by":"publisher","DOI":"10.1109\/AERO50100.2021.9438515"},{"key":"ref62","doi-asserted-by":"publisher","DOI":"10.1038\/s41467-021-23628-5"},{"key":"ref63","doi-asserted-by":"publisher","DOI":"10.1109\/URTC51696.2020.9668863"},{"key":"ref64","doi-asserted-by":"publisher","DOI":"10.1038\/s41586-021-03506-2"},{"key":"ref65","doi-asserted-by":"publisher","DOI":"10.3390\/s19132981"},{"key":"ref66","doi-asserted-by":"publisher","DOI":"10.1109\/cicc.2017.7993626"}],"event":{"name":"2023 IEEE High Performance Extreme Computing Conference (HPEC)","start":{"date-parts":[[2023,9,25]]},"location":"Boston, MA, USA","end":{"date-parts":[[2023,9,29]]}},"container-title":["2023 IEEE High Performance Extreme Computing Conference (HPEC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/10363430\/10363422\/10363509.pdf?arnumber=10363509","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,1,12]],"date-time":"2024-01-12T18:19:24Z","timestamp":1705083564000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10363509\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,9,25]]},"references-count":66,"URL":"https:\/\/doi.org\/10.1109\/hpec58863.2023.10363509","relation":{},"subject":[],"published":{"date-parts":[[2023,9,25]]}}}